Set/reset latch with minimum single event upset

Details Set/reset latch with minimum single event upset Set/reset latch with minimum single event upset

2005-07-14

2008-09-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S208000, C327S209000, C327S217000, C327S218000, C714S726000

Reexamination Certificate

active

07425855

ABSTRACT:
A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

REFERENCES:
patent: 5001361 (1991-03-01), Tamamura et al.
patent: 6008678 (1999-12-01), Barber
patent: 6373771 (2002-04-01), Fifield et al.
patent: 6433586 (2002-08-01), Ooishi
patent: 6624677 (2003-09-01), Wissel
patent: 6803799 (2004-10-01), Churchill et al.

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