Electrical computers and digital processing systems: memory – Storage accessing and control
Reexamination Certificate
1998-04-08
2001-03-20
Nguyen, Viet Q. (Department: 2818)
Electrical computers and digital processing systems: memory
Storage accessing and control
C711S102000, C711S103000, C711S148000, C711S167000, C700S005000, C712S232000, C365S230030, C365S194000
Reexamination Certificate
active
06205512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a monolithic integrated circuit comprising two memories that are preferably distinct from each other and electronic circuits making it possible for the two memories to work simultaneously.
It can be applied especially to electrically erasable and programmable non-volatile memories or EEPROMs, flash EPROMs or battery-saved memories. Each of the memory cells of these first two types of memories consists of a floating-gate transistor comprising a control gate, a floating gate, a source region and a drain region. To read or write in a memory cell of this kind, specific voltages are applied to connections that lead to these cells. These voltages depend on the types of memory.
2. Discussion of the Related Art
For example, to program a memory cell in an EEPROM memory, a high positive voltage is applied to the word line connected to the control gate of the floating-gate transistor of the memory cell and zero voltage is applied to the bit line connected to the drain region. The application of these voltages creates a high voltage across the narrow oxide layer. The result of this high voltage is the migration of electrons towards the floating gate. These electrons are trapped in the floating gate. This phenomenon is called a tunnel phenomenon.
In another example, to program a flash EEPROM type memory, the voltages applied to the various electrodes of a memory cell are different. During a programming operation, a positive high voltage is applied to the word line of the transistor of a memory cell. An intermediate voltage, for example a positive voltage of the order of 5 volts, is applied to the drain region. Just as in an EEPROM type memory, the application of these voltages prompts a migration of the electrons. This phenomenon is known as a hot carrier phenomenon.
There is therefore a certain degree of disparity between the programming and read voltages. This disparity exists for one and the same memory as well as for different types of memories.
On a monolithic integrated circuit that incorporates, in particular, different types of memories, it is sought however to preserve the possibility of simultaneous operation as if the two memories were not on the same integrated circuit. It is furthermore sought to use different types of memories on the same integrated circuit because the different types of memories lead to different characteristics: greater or lower writing speeds, integration density, bit-by-bit or page-by-page accessibility. A designer may then, with the same integrated circuit, have different possibilities available by which he can organize his work more efficiently.
There is a known way of having one integrated circuit with two memories that are distinct from each other. However, the possibility of executing simultaneous operations on these two memories is limited. Thus it is possible to read and write in a flash EPROM type memory while at the same time reading or writing in an EEPROM type memory, provided that all the useful functions are duplicated. This means the duplication of the buses and circuits to which they are connected. The problem that arises is that these functions then occupy far more space on the integrated circuit and reduce its efficiency. In particular, having two buses is a severe disadvantage. If there is only one bus, the working of the memories is not simultaneous; it is alternating. In that case, there is a loss of time.
SUMMARY OF THE INVENTION
The invention seeks to overcome this problem by enabling the operations of writing or reading in a memory at the same time as it enables writing or reading in another memory, these two memories being present on the same integrated circuit. Preferably, there is only one bus.
In practice, the invention proposes to overcome this problem by enabling the selection of either of the memories and the execution therein of writing or reading operations while the other memory is in read or write mode. The invention takes advantage of the fact that a programming or reading operation lasts for a certain predetermined amount of time, a duration that is specific to each memory. Rather than being encumbered by it, the operation uses the time during which a memory is busy with one of these tasks to isolate it, select the other memory and start making this other memory carry out a read or write operation. A selection signal is therefore used to begin a task. The continuation of the task is conditioned by a hold signal activated by this selection signal.
Thus, an object of the invention is to provide a monolithic integrated circuit comprising two memories that are distinct from each other, a microcontroller for the sequencing of write or read operations in these memories, and a selection circuit capable of selecting either of the memories and receiving a selection signal. According to the invention, the integrated circuit comprises two microcontrollers each linked with one of the memories, wherein each microcontroller has a circuit for the execution, in each memory, of the write or read operations independently of the value of the selection signal.
In one example, to resolve the problem of the specific voltages to be applied for a particular type of memory, load pumps have been duplicated. Thus, the assembly consisting of the microcontroller and the load pump is used to execute programming or read operations in each memory independently of each other.
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French Search Report for French application No. 9704285, filed Apr. 8, 1997.
Brigati Alessandro
Devin Jean
Leconte Bruno
Galanthay Theodore E.
Morris James H.
Nguyen Viet Q.
SGS-Thomson Microelectronics S.A.
Wolf Greenfield & Sacks P.C.
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