Set dominant latch with soft error resiliency

Details Set dominant latch with soft error resiliency Set dominant latch with soft error resiliency

2007-09-28

2009-08-04

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000, C326S009000, C326S098000, C327S208000, C327S218000

Reexamination Certificate

active

07570080

ABSTRACT:
A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the logical value of the storage node does not correspond a logical value of an output node. The logic circuit may be a set dominant latch and a memory circuit may be formed based on the set dominant latch.

REFERENCES:
patent: 6026011 (2000-02-01), Zhang
patent: 6046606 (2000-04-01), Chu et al.
patent: 6366132 (2002-04-01), Karnik et al.
patent: 2004/0095825 (2004-05-01), Tanizaki et al.
patent: 2004/0246782 (2004-12-01), Chu et al.
patent: 2005/0231257 (2005-10-01), Arima et al.
patent: 2006/0001442 (2006-01-01), Wood et al.
patent: 2006/0026457 (2006-02-01), Bernstein et al.
patent: 2006/0082404 (2006-04-01), Ishii et al.
patent: 2008/0120525 (2008-05-01), Agarwal

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