Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2008-03-04
2008-03-04
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S262000, C710S263000, C710S264000, C710S268000, C710S200000
Reexamination Certificate
active
10726351
ABSTRACT:
A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.
REFERENCES:
patent: 5446910 (1995-08-01), Kennedy et al.
patent: 5542076 (1996-07-01), Benson et al.
patent: 5708814 (1998-01-01), Short et al.
patent: 5790130 (1998-08-01), Gannett
patent: 5841444 (1998-11-01), Mun
patent: 5867687 (1999-02-01), Simpson
patent: 6023281 (2000-02-01), Grigor et al.
patent: 6078339 (2000-06-01), Meinerth et al.
patent: 6191800 (2001-02-01), Arenburg et al.
patent: 6259461 (2001-07-01), Brown
patent: 6266072 (2001-07-01), Koga et al.
patent: 6282601 (2001-08-01), Goodman et al.
patent: 6317133 (2001-11-01), Root et al.
patent: 6362818 (2002-03-01), Gardiner et al.
patent: 6445391 (2002-09-01), Sowizral et al.
patent: 6469746 (2002-10-01), Maida
patent: 6473086 (2002-10-01), Morein et al.
patent: 6570571 (2003-05-01), Morzumi
patent: 6571206 (2003-05-01), Casano et al.
patent: 6574693 (2003-06-01), Alasti et al.
patent: 6724390 (2004-04-01), Dragony et al.
patent: 6747654 (2004-06-01), Laksono et al.
patent: 6772189 (2004-08-01), Asselin
patent: 6781590 (2004-08-01), Katsura et al.
patent: 6813665 (2004-11-01), Rankin et al.
patent: 7043729 (2006-05-01), Lewis
patent: 2002/0144004 (2002-10-01), Gaur et al.
patent: 2002/0161957 (2002-10-01), Comeau et al.
patent: 2003/0101293 (2003-05-01), Stevens
patent: 2003/0128216 (2003-07-01), Walls et al.
patent: 2003/0140179 (2003-07-01), Wilt et al.
patent: 2003/0187914 (2003-10-01), Kaniyar et al.
patent: 2004/0075623 (2004-04-01), Hartman
patent: 2004/0111549 (2004-06-01), Connor et al.
patent: 2004/0122997 (2004-06-01), Diamant
patent: 2005/0012749 (2005-01-01), Gonzalez
patent: 2005/0088445 (2005-04-01), Gonzalez
patent: 0571969 (2003-05-01), None
“Advanced DPCs”, Microsoft Corporation, Nov. 1, 2006, retrieved from the Internet on Oct. 4, 2007 at http://www.microsoft.com/technet/sysinternals/information/advanceddpcs.mspx.
“Deferred Procedure Call”, Wikipedia.org, Sep. 19, 2007, retrieved from the Internet on Oct. 4, 2007 at http://en.wikipedia.org/wiki/Deferred—Procedure—Call.
“Lesson 8—Interrupt and Exception Handling”, Microsoft Corporation, 2007, retrieved from the Internet on Oct. 4, 2007 at http://www.microsoft.com/technet/archive/winntas/training
tarchitectoview
tarc—8.mspx.
Whitman, “Dynamic Load Balancing For Parallel Polygon Rendering” IEEE Computer Graphics and Applications, IEEE Inc. New York, U.S. vol. 14, No. 4, pp. 41-48, Jul. 1, 1994.
Molnar et al., “PixelFlow: HighSpeed Rendering Using Image Composition”, SIGGRAPH 92, pp. 231-240, unknown date.
Nvidia Corporation
Rinehart Mark H.
Zaman Faisal
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