Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-10-01
2004-03-02
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C711S103000, C711S163000, C710S306000, C710S311000, C710S312000, C710S313000, C365S230020
Reexamination Certificate
active
06701403
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to non-volatile memory, such as firmware, and more particularly to accessing such non-volatile memory, such as by a service processor.
2. Description of the Prior Art
Modem computer systems typically have firmware, or other non-volatile memory. Firmware is generally a category of memory chips that hold their content without electrical power and include read-only memory (ROM), programmable ROM (PROM), erasable and programmable ROM (EPROM) and electrically erasable and programmable ROM (EEPROM) technologies. Firmware becomes “hard software” when holding program code. For example, in some computer systems, the firmware may include the basic input/output system (BIOS) of a system. The BIOS is a set of routines in a computer, which is stored on a chip and provides an interface between the operating system and the hardware. The BIOS supports all peripheral technologies and internal services, such as the real-time clock.
The firmware or other non-volatile memory for a given computer system, such as those relying on chipset architectures designed by Intel Corp., of Santa Clara, Calif., may be located behind each of two different bridge controllers of the architecture. One of the bridge controllers, commonly referred to as the Northbridge controller, is the controller for the front-side bus that interfaces between the central processing units (CPUs) of the computer system, and all high-speed components, such as memory, the Accelerated Graphics Port (AGP) bus, and the Peripheral Component Interconnect (PCI) bus. The other bridge controller, commonly referred to as the Southbridge controller, stems from the PCI bus, and is the controller for Integrated Drive Electronics (IDE) drives and lower-speed ports, such as Universal Serial Bus (USB) ports, serial ports, audio ports, and so on. For other Intel chipset architectures, a memory controller hub (MHC) replaces the Northbridge controller, and an I/O controller hub (ICH) replaces the Southbridge controller, with similar, but not identical, functionality.
In multi-node computer systems, there are a number of nodes, each possibly having its own chipset architecture, CPUs, and so on, over which processing is distributed. Each node of the multi-node computer system further usually has a service processor, located behind the Southbridge controller. The service processor is typically responsible for handling maintenance and other service-oriented tasks for its node.
A difficulty with current chipset architectures, however, is that the service processor of a node only has access to firmware located on the Southbridge side of the node. That is, the firmware located on the Northbridge side of the node is inaccessible to the components located behind the Southbridge controller, such as the service processor. This means that the service processor cannot maintain the firmware located behind the Northbridge controller, which is problematic in situations where the service processor is responsible for such maintenance, such as in multi-node computer systems. For these described reasons, as well as other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to non-volatile memory access, such as firmware access by a service processor. In a method of the invention, a service processor asserts a controller signal to select either a first non-volatile memory, or a second non-volatile memory. The first non-volatile memory is located behind a first bridge controller and is otherwise accessible by the service processor. The second non-volatile memory is located behind a second bridge controller and is otherwise accessible only by a processor other than the service processor. The service processor then accesses the selected non-volatile memory, via a bus communicatively coupled to both the non-volatile memories.
A system of the invention includes a first and a second processor, a first and a second bridge controller, a first and a second non-volatile memory, and a control line. The first non-volatile memory is located behind the first bridge controller and is normally accessible by the first processor. The second non-volatile memory is located behind the second bridge controller and is normally accessible only by the second processor. The control line extends from the first processor and multiplexes the first and the second non-volatile memories, enabling the first processor to access both of these non-volatile memories.
An article of manufacture of the invention includes a computer-readable medium and means in the medium. The means is for asserting a control signal to access a desired non-volatile memory selected from a first and a second non-volatile memory. The first non-volatile memory is located behind a first bridge controller and normally accessible. The second non-volatile memory is located behind a second bridge controller and otherwise inaccessible. Other features and advantages of the invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5566344 (1996-10-01), Hall et al.
patent: 5872945 (1999-02-01), Wett
patent: 5968140 (1999-10-01), Hall
patent: 5999476 (1999-12-01), Dutton et al.
patent: 6052754 (2000-04-01), Anand
patent: 6112311 (2000-08-01), Beardsley et al.
patent: 6158015 (2000-12-01), Klein
patent: 6161157 (2000-12-01), Tripathi et al.
patent: 6256744 (2001-07-01), Simonich et al.
patent: 6272580 (2001-08-01), Stevens et al.
patent: 6321286 (2001-11-01), Goodrum et al.
patent: 2002/0083258 (2002-06-01), Bauman et al.
patent: 2002/0143967 (2002-10-01), Derr
patent: WO 01/24014 (2001-04-01), None
ETG White Paper, “A good thing in a small package: comparing the IBM eserver pSeries 640 to the Sun E420R,” Oct. 2000, prepared by Enabling Technologies Group, Inc., http://ww.etginc.com.
Bax Daniel H.
Lary Richard A.
Law Offices of Michael Dryja
Padmanabhan Mano
Song Jasmine
LandOfFree
Service processor access of non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Service processor access of non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Service processor access of non-volatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3185761