Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-09-28
2002-03-19
Ellis, Nevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06360295
ABSTRACT:
BACKGROUND
Frequently in the design of high speed electronic printed circuit boards there is a need to use a memory device as some sort of ‘hardware look up table’. This look up table sometimes contains the result of some mathematical computation that is pre-computed for all possible input values. This look up table technique is commonly used both in hardware and in software as a mechanism to improve some metric of system performance. The performance improvement results because, while the system is processing data, the system processor need not commit resources to performing the mathematical computation since the results have already been pre-computed and stored in the lookup table.
In the particular case of a hardware implementation of the look up table, it is frequently found that this lookup table is generally not accessible to a conventional processor in that the memory implementing the look up table is not interfaced to the processor's address, data, and control busses. Making the memory constituting the look up table accessible to the processor generally requires the addition of several components because now access to the memory device must be shared between the processor (for table loading) and the normal input data stream (for data processing).
FIG. 1
is a diagram of a conventional computer system
10
featuring the interface between a memory
15
and a CPU
11
. The memory device
15
hosts the look up table discussed above. All the other devices shown in
FIG. 1
are the additional parts, or overhead, necessary to allow a CPU/processor to access the memory. The transceivers
14
allow the processor to access the address and data pins of memory device
15
over address bud
12
and data bus
13
. If there are multiple such memory devices
15
, in general there will be a set of transceivers
14
for each memory device
15
. Even in the case of a single memory device
15
, there is considerable overhead in terms of additional parts that is associated with allowing a CPU
11
to access the memory
15
.
Another approach that could be used if providing access to a conventional processor is not possible or if there happens to be no conventional processor even available in the system is to use conventional ‘read only’ memory (ROM). ROM devices are non-volatile in that they retain data when power is turned off, and typically are programmed only once before the device is assembled onto the printed circuit board.
A second application where it may be desirable to have serially loadable memory is one where a processor has access to non-volatile but re-writable memory which is critical to being able to bring the system that contains the processor into an operational state. An example of such memory would be the BIOS memory on a conventional personal computer. One of the functions of the BIOS memory is to contain ‘boot code’ which is a program that the processor reads from BIOS memory and executes upon receipt of a system start or reset. Obviously corruption of this program could cause the computer to be unable to be brought up into a functional state. However, if this program is contained in non-volatile but re-writable memory, as is generally the case with modern personal computers, then there is a chance that an errant or malicious software program could overwrite this critical memory area. Although there are several mechanisms available to make this scenario less probable, the only fail-safe way to both have the advantages of re-writable non-volatile memory without the risk of having an unbootable system is to have a separate non-volatile but not writable memory device which contains a boot code program that can be used as an emergency boot device if the normal boot memory device gets corrupted. This however requires a second physical memory device to be installed in the system. However, not providing a second read only memory device adds some risk to the system. Providing access to a serially loadable memory device, in certain circumstances, would be a more cost effective solution. For a further discussion on the comparative advantages of this invention refer to the section titled “Advantages of this Invention over Current Practice”.
SUMMARY OF THE DISCLOSURE
The invention provides a serial load controller for loading at least one input data bit serially into a memory. The memory is interfaced to a data bus and an address bus. The serial load controller includes a counter generating an internal address pointer signal in response to a first control signal. The first control signal indicates that the input data bit is to be transferred serially into the memory. The counter is responsive to the first control signal to reset the internal address pointer to an initial value. A multiplexer is coupled to select one of the address bus and the internal address pointer signal as an output address bus in response to the first control signal. Means, such as suitable transceiver or other bus driver, are provided for driving at least a first data bit onto the data bus in response to the clock pulse.
REFERENCES:
patent: 4541075 (1985-09-01), Dill et al.
patent: 4811295 (1989-03-01), Shinoda
patent: 5864568 (1999-01-01), Memazie
XILINX Product Specification (Sep. 17, 1999).
Lattice Semiconductor Webpage (Printed Sep. 27, 1999).
Ellis Nevin L.
Starr Mark T.
Unisys Corporation
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