Serially interfaced random access memory

Details Serially interfaced random access memory Serially interfaced random access memory

2010-09-20

2011-12-13

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C711S104000, C365S063000

Reexamination Certificate

active

08078789

ABSTRACT:
A serially interfaced massively parallel Random Access Memory (RAM) includes a matrix of control logic sections on one integrated circuit die, augmented by a switching matrix with an external interface to multiple high speed serial signaling means. A matrix, of the same dimension, of dense memory element arrays is implemented on a different integrated circuit die. One control logic section die and one or more others containing memory sections are joined by appropriate means to form one integrated circuit stack, implementing a matrix of independent memory units. The switching matrix translates command and data content encoded on the external signaling means bidirectionally between internal data and control signals and connects these signals to the control logic sections. Each independent memory unit ably performs atomic read-alter-writes to enable software mutual exclusion operations (MUTEXes). Each and every matrix may guard against defects by having additional rows and/or columns.

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