Serializer-deserializer circuit having increased margins for...

Details Serializer-deserializer circuit having increased margins for... Serializer-deserializer circuit having increased margins for...

2002-12-12

2004-03-23

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000

Reexamination Certificate

active

06710726

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high data rate (HDR) communication system, and more particularly, to a serializer-deserializer circuit having increased margins for setup and hold time.
2. Discussion of Related Art
Serializer-deserializer circuits that are essential to an HDR communication system receive parallel data and convert it into serial data, or receive serial data and convert it into parallel data, and transfer this converted data at high speed. In general, serializer-deserializer circuits use a clock signal, which is locked to and input with an input data signal, as a reference clock of a phase locked loop (PLL).
FIG. 1
is a block diagram of a conventional serializer-deserializer circuit. Referring to
FIG. 1
, a serializer-deserializer circuit
10
includes a data skew control circuit
20
, a latch circuit
30
, a serial converter circuit
40
, and a PLL
50
. The PLL
50
operates by receiving a clock signal TBC to which a data signal TXD is locked. The PLL
50
outputs a reference clock signal TBCREF having the same frequency as the clock signal TBC, to the latch circuit
30
.
The data skew control circuit
20
receives the data signal TXD in response to the reference clock signal TBCREF to control the skew of the data signal TXD and outputs a data signal DTXD to the latch circuit
30
. The latch circuit
30
receives and latches the signal DTXD, which is locked to the reference clock signal TBCREF, and outputs a latched signal LDTXD. The serial converter circuit
40
serializes and outputs the signal LDTXD in response to the reference clock signal TBCREF.
Here, the clock signal TBC, which is locked to the data signal TXD and input together to the serializer-deserializer circuit
10
with the data signal, is usually not a clean signal generated from an oscillator, but has coarse characteristics, such as peak-to-peak jitters of over 100 picoseconds (ps). The PLL
50
which operates and generates signals based on the clock signal TBC has coarse characteristics as well.
Under HDR conditions where there is a transfer rate of several gigabits per second (Gbps), the overall characteristics of a communication system are affected by the jitter characteristics of an output signal from a PLL used in the communication system. Consequently, improving the jitter characteristics of the output signal from the PLL improves noise, setup and hold margins, etc, thereby improving system performance.
SUMMARY OF THE INVENTION
The present invention is directed to a serializer-deserializer circuit having improved transfer characteristics using a clock signal, which is generated by an oscillator, as an input signal to a phase locked loop (PLL), instead of using a clock signal locked to a data signal as the input signal to the PLL.
A serializer-deserializer circuit according to a first embodiment of the present invention includes a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). Here, the data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal.
The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes the delayed data signal output from the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal.
Preferably, the data skew control circuit includes a first delay circuit, a second delay circuit, and a selection code signal generation circuit. Here, the first delay circuit receives and delays the first clock signal in response to an m-bit selection code signal (where m is a natural number) to generate a second clock signal. The second delay circuit receives and delays a data signal in response to the selection code signal to generate the delayed data signal.
The selection code signal generation circuit receives the reference clock signal and the second clock signal, and varies the logic value of the selection code signal until a phase of the reference clock signal is the same as that of the second clock signal to fix the logic value of the selection code signal.
The first delay circuit includes a delay buffer unit having a plurality of buffers that are connected in serial, wherein a first buffer receives the first clock signal, and a selection circuit for selecting an output of one of the buffers in response to the selection code signal and outputting the selected signal as the second clock signal.
The selection code signal generation circuit includes a first flip-flop for receiving and outputting the second clock signal in response to the reference clock signal, a second flip-flop for receiving and outputting the output of the first flip-flop in response to the reference clock signal, an exclusive OR unit for performing an exclusive OR operation on the outputs of the first and second flip-flops, and an up/down counter for increasing and decreasing the logic value of the selection code signal in response to the output of the exclusive OR unit. The second delay circuit is the same as the first delay circuit. The period of the first clock signal is the same as that of the reference clock signal.
The latch circuit latches the data signal at falling edges of the reference clock signal when the data signal has a first speed, and the latch circuit latches the data signal at falling edges of a clock signal having twice the frequency as the reference clock signal when the data signal has a second speed. The PLL outputs the reference clock signal and the clock signal having twice the frequency as the reference clock signal. The external reference clock signal is generated by an oscillator.
A data skew control circuit according to a second embodiment of the present invention includes a first delay circuit, a second delay circuit, and a selection code signal generation circuit. Here, the first delay circuit receives and delays a first clock signal in response to an m-bit selection code signal (where m is natural number) to generate a second clock signal. The second delay circuit receives and delays a data signal in response to the m-bit selection code signal to generate a delayed data signal.
The selection code signal generation circuit receives a reference clock signal and the second clock signal and varies the logic value of the selection code signal until a phase of the reference clock signal is the same as that of the second clock signal to fix the logic value of the selection code signal.
The first delay circuit includes a delay buffer unit having a plurality of buffers that are connected in serial, wherein a first buffer receives the first clock signal, and a selection circuit for selecting an output from one of the buffers in response to the selection code signal and outputting the selected signal as the second clock signal.
The selection code signal generation circuit includes a first flip-flop for receiving and outputting the second clock signal in response to the reference clock signal, a second flip-flop for receiving and outputting the output of the first flip-flop in response to the reference clock signal, an exclusive OR unit for performing an exclusive OR operation on the outputs of the first and second flip-flops, and an up/down counter for increasing and decreasing the logic value of the selection code signal in response to the output of the exclusive OR unit.
The second delay circuit is the same as the first delay circuit and the period of the first clock signal is the same as that of the reference clock signal. The reference clock signal is generated by a PLL, which is operated in response to an external reference clock signal generated from a predetermined oscillator.
According to preferred embodiments of the present invention, rather than using the first clock signal input with the data signal, the serializer-deserializer circuit uses a signal,

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