Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1998-12-15
2002-09-03
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S519000, C345S567000
Reexamination Certificate
active
06445394
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to systems and methods for accessing memory, and more particularly to systems and methods for providing access to a common memory for multiple memory controllers.
BACKGROUND OF THE INVENTION
In video graphics controller chips and other chips that employ memories, many different memories may be distributed throughout a die. For example, with conventional video graphics controller chips, there may be separate memory for a display buffer, color converter and other functions. These memories typically are different sizes having differing numbers of address and data lines. Moreover, there are typically separate memory controllers for each type of memory. Some memories may be single port, dual port or tri-port memories. Each may use differing access formats or have a different clock for each memory. Consequently, there is an extended amount of overhead in terms of logic circuitry that is required for each portion of distributed memory. Such overhead logic may include, for example, decoders, drivers, control logic and other circuitry. Also, when connecting the controllers to respective memories, or when connecting one controller to multiple memories, a problem arises in having enough die space to route the appropriate buses. Due to the cost of such logic and the desire to increase the speed of operation, it is desirable to minimize the length of the bus lines as well as the number of bus lines, if possible. However, with the distributed memory of the different memory types, graphics controller chips and other chips have accumulated complex layout designs and additional memory control overhead circuitry.
Some graphics controller chips are known that have embedded memory as opposed to external memory, but the embedded memory again is typically designed to have an unnecessary amount of complexity in terms of redundant circuitry. In addition, such embedded systems often have distributed memories such as different size buffers for differing functionality performed by the graphics controller chip. For example, one memory may have a bit width of 64 bits and another memory may have a bit width of 128 bits. Therefore, a system can have difficulty sharing data between memories directly or when they need to multiplex data from the differing memories. For example, there may be a desire to use the same data in memory by differing circuitry such as a display engine and a 3D drawing engine. However, these engines may require data at different rates and over different buses.
One suggested solution has been to combine memories into one memory. However, such designs may include, for example, a memory having a wider data width than practically desirable. For example, if all graphics controller engines require access to a memory, data may have to be transferred on the order of 10 gigabits per seconds or more. In order to move data in and out of such a memory, the memory width will typically have to be very wide which will subsequently require, for example, an unnecessarily high number of address lines.
In addition, the use of serialization to reduce electromagnetic interference is known. For example, for chip to chip serial communication a low voltage differential swing (LVDS) communication standard designed by National Semiconductor, Inc. uses serializers to communicate red, green and blue (RGB) data (and other data if desired) to reduce electromagnetic interference. However, such applications are not typically used to facilitate the combination of memory access for multiple controllers.
Another memory access mode, sometimes referred to as page mode, can provide very high memory throughput at peak times, however, it is not typically capable of sustaining its peak throughput continuously across page boundaries and has a limited page size. So at higher throughputs, if an address in on another page, it can take long time periods to switch pages to obtain the data.
Consequently, there exists a need for an improved memory system for use with integrated circuits to reduce redundancy from distributed memory configurations. It would be desirable if such a system facilitated a high band width transfer of data using a smaller data bus to facilitate communication of information from a common memory to multiple controllers.
REFERENCES:
patent: 5894586 (1999-04-01), Marks et al.
Aleksic Milivoje M.
Chow Hugh
Hartog Adrian
ATI International SRL
Tung Kee M.
Vedder Price Kaufman & Kammholz
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