Serial to parallel data input methods and related input buffers

Details Serial to parallel data input methods and related input buffers Serial to parallel data input methods and related input buffers

2003-01-07

2004-11-16

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S230080

Reexamination Certificate

active

06819616

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory devices, and more particularly, to data input methods and buffers for semiconductor memory devices.
BACKGROUND OF THE INVENTION
In a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), tDQSS is defined to provide successful write operations. Here, tDQSS denotes a delay time between a first rising edge of data strobe signal (DQS), and a rising edge of a clock to which a write command is input.
A DDR SDRAM may be required to normally perform write operations in a minimum tDQSS or a maximum tDQSS. The standard specification provides that the minimum tDQSS is 0.75 tCK, and the maximum tDQSS is 1.25 tCK. Here, tCK indicates a time required for a clock cycle, and a tDQSS window denotes a difference between the maximum tDQSS and the minimum tDQSS.
FIG. 1
is a circuit diagram of an example of a conventional data input buffer. Referring to
FIG. 1
, a data input buffer
10
divides serial data PDINT into even data E
1
and E
2
and odd data O
1
and O
2
, and outputs the even and odd data in response to a data strobe signal PDS and control signals PDSEN
1
and PDSEN
2
.
The even data E
1
and E
2
are output to a data input line DI_E in response to an internal clock signal PCLK and a control signal PCLKEN
1
, and the odd data O
1
and O
2
are output to a data input line DI_
0
in response to the internal clock signal PCLK and a control signal PCLKEN
2
.
The data input buffer
10
includes a plurality of inverters and a plurality of transmission gates, which may require a very large layout area.
FIG. 2
is a circuit diagram of another example of a conventional data input buffer. Referring to
FIG. 2
, a data input buffer
20
divides serial data PDINT into even data and odd data, and latches the even and odd data in response to a data strobe signal PDS. The latched data is output to data input lines DI_E and DI_
0
.
A tDQSS window of the data input buffer
20
, however, may be so small that it may barely satisfy requirements of the standard specification. Therefore, the data input buffer
20
may not normally perform write operations in the minimum tDQSS and the maximum tDQSS.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, methods of buffering data for an integrated circuit memory device can include converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits. The first even and odd data bits from the first and second conversion output nodes can be provided at first and second latch output nodes during a first period of time, and the second even and odd data bits from the first and second conversion output nodes can be provided at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping. The first even and odd data bits can be latched at first and second buffer output nodes responsive to providing the first even and odd data bits at the first and second latch output nodes. The second even and odd data bits can be latched at the first and second buffer output nodes responsive to providing the second even and odd data bits at the third and fourth latch output nodes.


REFERENCES:
patent: 4386367 (1983-05-01), Peterson et al.
patent: 6178139 (2001-01-01), Hirobe et al.
patent: 6229757 (2001-05-01), Nagata et al.
Samsung Electronics: “Key Points for Controller Design” DDR SDRAM/SGRAM Application Note, MPP-JLEE-Q4-98.

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