Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-03-16
2004-02-03
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S005000
Reexamination Certificate
active
06687769
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a serial peripheral interface for use in microcontroller-based products. More particularly, the present invention relates to a high performance buffering scheme for a serial peripheral interface that facilitates high data transmission rates between microprocessors, components and other devices.
BACKGROUND OF THE INVENTION
The demand for higher performance, microcontroller-based products for use in communication and processing applications continues to increase rapidly. As a result, microcontroller-based product manufacturers are requiring for the components and devices within these products to be continually improved to meet the design requirements of a myriad of emerging audio, video and imaging applications.
These microcontroller-based products use various types of processors, for example, general purpose microprocessors for controlling the logic of various digital devices, such as clock radios, microwave ovens, digital video recorders and the like, and special purpose microprocessors, such as math coprocessors for mathematical computations, or digital signal processors used in manipulating various types of information, including sound, imaging and video information. For the transmitting and receiving of data between various devices and components, microprocessors and other devices utilize various types of serial interfaces. One such type of interface definition typically used is the serial peripheral interface (SPI). In addition, for the temporary storage of data, for example, to permit the microprocessors to manipulate the data before transferring the data through the SPI to another device, the microprocessors generally utilize one or more buffers. These buffers are configured with the SPI's to enable the processors to transmit and receive data to and from the buffers as needed in an application.
With reference to
FIG. 1
, an SPI configuration
100
, which comprises a synchronous, three-wire interface, can be generally configured within a master device
102
, such as a microprocessor device, and a slave device
104
, such as an analog-to-digital converter or similar peripheral device, to permit the two devices to communicate data in between. In master device
102
, the SPI comprises a buffering scheme including a master shift register
106
. In addition, master device
102
includes a clock generator
108
. The least significant bit of master shift register
106
includes an input connected to a master out/slave in (MOSI) pin and the most significant bit of master shift register
106
includes an output connected to a master in/slave out (MISO) pin. The clock generator
108
includes an output connected to the clock input of master shift register
106
and to the S clock (SCK) pin.
Meanwhile, in slave device
104
, the SPI comprises a buffering scheme including a slave shift register
110
. The least significant bit of slave shift register
110
includes an input connected to a MISO pin and the most significant bit of slave shift register
110
includes an output connected to a MOSI pin. The clock input of slave shift register
110
is connected to an SCK pin. Although one slave device
104
is illustrated, more than one slave device can be coupled to master device
102
. In addition, the respective MOSI, MISO, and SCK pins of master device
102
and slave device
104
can be connected together.
Both master device
102
and slave device
104
include a separate data path to permit entering data to be transmitted into and retrieving data from shift registers
106
and
110
. Further, both master device
102
and slave device
104
typically have status register bits for indicating the current status of the interface and control register bits for configuring the interface. In addition, one or more chip select signals
112
of master device
102
and connected to enable various inputs of slave device
104
.
Various drawbacks exists for such an SPI interface. For example, a single data transfer is generally limited to the number of bits which can be held in the SPI shift register, for example, 8 bits. On each occasion that a data transfer is commenced, the CPU must write the byte to be transferred to the appropriate shift register and then assert a control bit to commence the serial transfer of data or the reading of received data. Thus, the data throughput of such an SPI is limited.
Further, such an SPI configuration requires a relatively high degree of intervention from the central processing unit (CPU) or other master controller device, instead of permitting the CPU to be servicing demands from a plurality of other slave components and devices, i.e., the SPI requires high interrupt overhead within the CPU. For example, once a data transfer is complete, the SPI typically interrupts the CPU to demand further servicing, such as the loading of a new byte of data for transmission, or the CPU may be configured for continually polling the SPI to determine if such further servicing is required. As a result, the required CPU intervention for each byte transferred is substantial and the frequency with which the CPU must dedicate its resources to servicing the SPI is quite high.
Various attempts have been made at addressing the various problems above, such as a lower than desired data rate and a higher CPU overhead. Some attempts have included the increasing in size of the buffers to obtain a higher data rate. For example, with reference to
FIG. 2
, a double buffering configuration
202
incorporated within an SPI scheme
200
includes an 8-bit receive data buffer
204
for the temporary receiving of data and a dual purpose, transmit/receive shift register
206
. Unfortunately, the increased double buffer size results in increased logic area, i.e., this SPI buffering scheme requires additional logic to be implemented to make operational, resulting in a higher bit rate, but also resulting in greater logic area requirements. In addition, more power consumption is required for such a double buffering arrangement. Still further, this SPI buffering scheme also results in very high overhead since the CPU needs to read the data at least every two bytes received, because the buffer can only handle one byte at a time.
For example, once a single transaction is completed, SPI scheme
200
must have the next data ready for the CPU to write the data to transmit shift register
206
in buffering configuration
202
, i.e., since the CPU writes the data on every transaction, the SPI must be configured to transmit the data at the same time. Accordingly, since the CPU must write every single line of data, the CPU is required to service the SPI at a high frequency, instead of being able to operate or service other devices. Further, since the CPU has to frequently poll the peripheral devices, the resulting bit rate is fairly low, e.g., less than 1 Mhz.
Other attempts at solving the above problems have included trying to increase the CPU clock frequencies to increase the SPI bit rate; however, such configurations have high costs due to the need for more expensive CPU cores. In other words, prior art attempts to achieve a high performance SPI have resulted in an improvement of the performance of the SPI with respect to one aspect or problem, but have resulted to the detriment of the performance of the SPI with respect to other aspects or problems.
Accordingly, a need exists for an improved, high performance buffering scheme for a serial peripheral interface to provide an increased serial transmit and receive data bit rate, while minimizing the logic area. In addition, a need exists for an improved buffering scheme for reducing the amount of CPU polling or interrupt overhead required.
SUMMARY OF THE INVENTION
The serial peripheral interface and high performance buffering scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, an improved high performance buffering scheme is provided with a serial peripheral interface (SPI) to enable microcontroll
Brady W. James
Huynh Kim
Swayze, Jr. W. Daniel
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