Serial memory interface using interlaced scan

Details Serial memory interface using interlaced scan Serial memory interface using interlaced scan

1996-04-26

1998-05-19

Pan, Daniel H.

Excavating

371 2232, 371 2233, G01R 3128, G06F 1122

Patent

active

057547580

ABSTRACT:
A serial memory interface includes a register having a plurality of flip-flops forming a scan chain and coupled to both the input and output terminals of memory cells. An interlaced scan is established by interconnecting scan chains between multiple memory blocks. The interface structure provides a means for efficiently performing a built-in self test of an embedded memory while requiring minimal overhead in hardware structure.

REFERENCES:
patent: 4733405 (1988-03-01), Shimizume et al.
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
patent: 5469445 (1995-11-01), Nicolaidis
patent: 5621740 (1997-04-01), Kamada
Benoit Nadeau-Dostie et al., "Serial Interfacing for Embedded-Memory Testing", IEEE Design & Test of Computer, 1990, pp. 2-13.

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