Serial memory device provided with high-speed address control ci

Details Serial memory device provided with high-speed address control ci Serial memory device provided with high-speed address control ci

1989-05-30

1991-01-29

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365240, 371 102, G11C 800

Patent

active

049891812

ABSTRACT:
A semiconductor memory device having a serial access port and an improved redundant structure which can operate at a high speed is disclosed. The memory device comprises a normal memory cell array, a redundant memory cell array, a serial selection circuit for serially selecting data stored in the normal cell array in response to a control signal, a defective location memory for storing address of a defective memory cell or cells in the normal memory cell array, a counter incremented by the control signal for indicating the address selected by the serial selection circuit, a control circuit for selecting the redundant memory cell array when the content of the counter coincides with the content of the defective location memory, a plus-one circuit for generating an initial address which is larger than external initial address by one, and a count-up control circuit for applyig the control signal to the counter from its second occurrence after the application of the external initial address.

REFERENCES:
patent: 4701887 (1987-10-01), Ogawa

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