Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-05-03
2011-05-03
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S034000, C326S086000, C326S090000
Reexamination Certificate
active
07936180
ABSTRACT:
The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver.
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patent: 6617888 (2003-09-01), Volk
patent: 2004/0183565 (2004-09-01), Viehmann et al.
patent: 2008/0024178 (2008-01-01), Kim et al.
patent: 2008/0037617 (2008-02-01), Tang et al.
patent: 2008/0137721 (2008-06-01), Hsu et al.
patent: 2009/0051389 (2009-02-01), Nguyen
Chao Kuan-Hua
Chiu Pao-Cheng
Hung Chih-Chien
Mediatek Inc.
Thomas / Kayden
Tran Anh Q
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