Serial link scheme based on delay lock loop

Details Serial link scheme based on delay lock loop Serial link scheme based on delay lock loop

2006-09-26

2006-09-26

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S326000, C375S327000, C375S360000, C375S362000, C375S371000, C341S050000, C341S059000, C341S060000, C341S061000

Reexamination Certificate

active

07113560

ABSTRACT:
A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

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