Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-05-31
2003-03-18
Wong, Peter (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06535948
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a serial interface unit in the field of microelectronics. In particular, the invention relates to a serial interface unit that is capable of facilitating the communication of data between a data stream and multiple processors.
DESCRIPTION OF THE RELATED ART
Processors traditionally receive data through serial input/output (I/O) units or ports. Each processor typically has at least one designated I/O port, each port having a number of input pins and a number of output pins. An enhanced serial I/O unit (ESIO) designed by Lucent Technologies and included in Lucent's DSP16210 digital signal processor is exemplary of prior art serial I/O units. The ESIO is a programable, hardware-managed, double-buffered, full-duplex serial I/O port designed to support multi channel I/O processing on a time-division multiplex information highway. It has a four-pin input interface and a five-pin output interface. The ESIO communicates I/O buffer status to the processor core using input buffer full, output buffer empty, and other interrupt signals.
The ESIO contains 16 memory-mapped, double-buffered serial-to-parallel input demultiplexor registers. These 16-bit registers can be configured to demultiplex a maximum of 16 logical input channels. A logical input channel is a non-overlapping sequence of a fixed length of consecutive bits identified by a starting bit position within a frame of data.
The ESIO also contains 16 memory mapped, double-buffered parallel-to-serial output multiplexor registers. These 16-bit registers can be configured to multiplex a maximum of 16 logical output channels. Similar to the logical input channel, the logical output channel is a non-overlapping sequence of a fixed length of consecutive bits identified by a starting bit position within the frame.
Prior art serial I/O units, such as the ESIO, convert serial data from a data stream into parallel data for processing by a processor, and also convert parallel data from the processor into serial data which is returned to the data stream. However, in the prior art, each processor has a distinct, designated serial I/O unit. Generally, serial I/O units and their associated processors are contained within a single computer chip. Thus, integrated circuits specifically designed to accommodate a multitude of processors necessarily would also contain an associated serial I/O unit or port for each processor.
A need exists in the art of microelectronics for an integrated circuit capable of servicing multiple processors irrespective of the number of processors or processor types. The present invention addresses this need by providing a serial interface unit having a source request module for selecting one of at least two processors prior to transmitting data between the selected processor and a data stream. The invention further provides a method for transmitting and receiving data between a data stream and multiple processors using a destination request module.
SUMMARY OF THE INVENTION
The invention relates to a serial interface unit for processing data and a method therefor. In one embodiment, the serial interface has an input shift register and a destination request module. The input shift register is connected to at least two processors and is adapted to receive a serial input data from a serial data stream. Upon receipt of the serial input data, the input shift register converts it into parallel input data. Preferably, an input data buffer is connected between the input shift register and the at least two processors. The destination request module is connected to the input shift register and communicates with one of the at least two processors in response to an input shift register status signal and a processor designation signal. In the embodiment that includes the input data buffer, the destination request module communicates with one of the at least two processors in response to an input buffer status signal and the processor designation signal.
In another embodiment, the serial interface unit has a source request module and an output shift register. The output shift register is in communication with at least two processors and is adapted to receive a parallel output data from at least one of the processors. Preferably, an output data buffer is connected between the at least two processors and the output shift register. The source request module is in communication with the output shift register and communicates with one of the processors in response to an output shift register status signal and a processor designation signal. In the embodiment that includes the output data buffer, the source request module communicates with one of the at least two processors in response to an output buffer status signal and the processor designation signal. The output shift register is adapted to receive the parallel output data from at least one of the processors and convert the parallel output data into serial output data.
In either of the embodiments, the processor may be a digital signal processor, a microprocessor or a microcontroller.
In another embodiment, at least one of the serial interface units mentioned above may have a processor selection unit in communication with the request module. The processor selection unit provides the processor designation signal to the request module. The processor selection unit may further have a multiplexor, a channel counter and a processor selection register. The multiplexor supplies the processor designation signal to the request module. The channel counter is in communication with the multiplexor and provides a predetermined one of a plurality of channel counts to the multiplexor. The processor selection register is in communication with the multiplexor, the processor selection register providing the multiplexor with a processor identification information for each of the plurality of channel counts. The processor designation signal, in a preferred embodiment, comprises the processor identification information corresponding to the predetermined channel count.
The invention further contemplates a method for processing serial input data. One method of the invention comprises the steps of receiving the serial input data from a serial data stream, converting the serial input data into parallel input data, communicating the parallel input data directly to a data bus, or optionally via an input data buffer to the data bus, generating an input shift register full signal when the input shift register contains the parallel input data, or in the embodiment having an input data buffer, generating an input buffer full signal when the input data buffer contains the parallel input data, receiving the input shift register full signal at a destination request module, or in the embodiment having an input data buffer, receiving the input data buffer full signal at a destination request module, generating a processor designation signal representing a designated processor, receiving the processor designation signal at the destination request module, sending a service request to the designated processor, and receiving the parallel input data at the designated processor via the data bus.
Another method of the invention comprises the steps of viewing a status of an output shift register, generating an output shift register empty signal when the output shift register is without parallel output data, receiving the output shift register empty signal at a source request module, generating a processor designation signal representing a designated processor, receiving the processor designation signal at the source request module, sending a service request to the designated processor, applying the parallel output data to a data bus, receiving the parallel output data at the output shift register via the data bus, and converting the parallel output data into serial output data.
The invention further contemplates a method for substantially simultaneously processing serial input data from a serial data stream and parallel output data from at least two processors via a serial interf
Burroughs William G.
Webb Andrew Lawrence
Wheeler Paul Kurt
Agere Systems Inc.
Glass David
Ryan & Mason & Lewis, LLP
Wong Peter
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