Serial input/output semiconductor memory

Details Serial input/output semiconductor memory Serial input/output semiconductor memory

1991-09-18

1992-05-26

Bowler, Alyssa H.

Static information storage and retrieval

Recirculation stores

36518912, 365221, 365 78, G11C 700, G11C 804, G11C 11407

Patent

active

051173883

ABSTRACT:
A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a serial data register which includes a number of bit cells corresponding to one word of the memory cell array, a decoder for decoding an address signal and for successively making an access to each bit cell of the serial data register based on a decoded result, a register group comprising m+1 shift registers in correspondence with each digit of the address signal, where each of the shift registers comprise n registers which are connected to form a loop and m and n are integers satisfying m.gtoreq.0 and n>2, a shift circuit for shifting a content of one of the shift registers corresponding to a least significant digit of the address signal in response to a clock signal, and a transfer circuit for transferring a carry information which is received from a first arbitrary one of the shift registers to a second arbitrary one of the shift registers. The first arbitrary shift register corresponds to an ith most significant digit of the address signal, the second arbitrary shift register corresponds to a (i+1)th most significant digit of the address signal, and output signals of the shift registers are used as the address signal.

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