Serial DRAM controller with multi generation interface

Details Serial DRAM controller with multi generation interface Serial DRAM controller with multi generation interface

1990-01-19

1991-07-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 1300

Patent

active

050330276

ABSTRACT:
A DRAM controller which can be directly connected, without any automatic or selected reconfiguration, to DRAMs of various sizes. The externally-received address bits are remapped, so that the most significant two bits of the externally-received address bits are remapped onto the most significant bit of a row address and the most significant bit of a column address. This controller also provides selectable refresh periods.

REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.

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