Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2000-03-27
2004-08-17
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S004000, C710S003000
Reexamination Certificate
active
06779046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a serial-data transfer system for transferring serial data between at least one master device and slave devices.
2. Description of Related Art
Data communication may be performed in units of 8-bit data (1-byte data), for example, between a microcontroller and its peripheral devices. As is represented by, for example, an IIC(I
2
C)-bus (inter-IC control bus (which is simply referred to as an IIC bus, hereinbelow)), a serial-data transfer system serially transfers data between a master device that transfers data in units of 8-bit data and a plurality of slave devices.
In a serial-data transfer system that uses the aforementioned IIC bus, a master device on a controlling side, for example, a microcontroller, and a plurality of slave devices on the controlled side, for example, peripheral devices, are connected to each other via two two-way serial lines connected to a power source via pull-up resistors. The serial lines are a serial-data line (SDA) for transferring data and a serial-clock line (SCL) for transferring clock signals that control the data transfer.
Basically, the serial data line varies while the serial clock signal SCL is at a low level. While the signal SCL is at a high level, if the serial data line varies from a high level to the low level, it represents a start signal (START) for starting data transfer. If the serial data line varies from the low level to the high level, it represents a stop signal (STOP) for terminating the data transfer.
The master device first outputs a 1-bit start signal to the serial data line. Subsequently, it outputs 8-bit data serially in the order from the most significant bit (MSB) to the serial data line. The 8-bit data consists of a 7-bit inherent address that is uniquely preallocated to each of the slave devices and a subsequent 1-bit data-control signal that represents one of commands for a data-write to each of the slave devices and for a data-read therefrom.
The individual slave devices serially receive the 8-bit data outputted by the master device to the serial data line in synchronization with clock signals fed from the serial-clock line. Then, each of the slave devices compare the data with their own preallocated inherent address. As a result, the slave device having the inherent address that matches the data outputs acknowledge signal (affirmative response signals).
The master device verifies the acknowledge signal that the individual slave device outputted to the serial data line, then, serially outputs the 8-bit data, which will be transferred, to the serial data line when data-write to the slave device is required. The slave device that outputted the acknowledge signal serially receive the 8-bit data outputted from the master device to the serial data line, and then, similarly output the 1-bit acknowledge signal.
The master device transfers data consisting of a predetermined number of bytes depending on the requirement. Thereafter, the master device outputs 1-bit stop signal to the serial data line, and the slave device receives the stop signal and verifies termination of the data transmission. Thereafter, similarly, the master device serially specifies the slave device and repeats the data transfer.
In the serial-data transfer system employing the IIC bus, the plurality of slave devices must be accessed one by one. Therefore, even in a case of transferring data including the same control signal, such as a start, stop, or abort signal, which controls a plurality of the identical devices to be connected to the identical slave devices, the plurality of slave devices cannot be concurrently controlled.
To solve the problems, conventional serial-data transfer system take countermeasures such as having the control signals directly connected from the master device to individual apparatuses connected to a plurality of the slave devices for concurrent control purposes. Or, when concurrent control cannot be performed, an alternative counter measure taken is having the frequency of clock signals fed from a SCL increased, thereby transferring data to the plurality of slave devices so as to reduce the difference in time for control.
However, when the master device is directly connected to the apparatuses connected to the slave devices, in addition to the serial data line and the serial-clock line, the number of the lines must be increased, thereby decreasing advantages in the serial data transfer. Even when the frequency of the clock signal is increased, since the same data is repeatedly transferred to the individual slave devices, longer transfer time is required in proportion to increase in the number of the slave devices.
SUMMARY OF THE INVENTION
In view of the problems with the conventional art, an object of the present invention is to provide a serial-data transfer system that allows a master device to transfer the same data to a plurality of slave devices.
To achieve the above object, according to one aspect of the present invention, there is provided a serial-data transfer system wherein at least one master device on a controlling side and a plurality of slave devices on a controlled side are connected via a serial-data line for transferring data and a serial-clock line for transferring clock signals which control the data transfer; in a normal mode, address information corresponding to an inherent address of each of the slave devices is transmitted from the master device to each of the slave devices, and interactive data communication is performed between the master device and the slave device having an inherent address matching the address information; and in a local mode, address information corresponding to a common address is transmitted from the master device to a plurality of the slave devices which is intended to be specified, thereby specifying the plurality of the slave devices and concurrently transmitting the same data to the plurality of the slave devices.
Also, according to the present invention, there is provided a serial-data transfer system comprising a serial-data line for transferring data; a serial-clock line for transferring clock signals which control the data transfer; at least one master device on a controlling side and a plurality of slave devices on a controlled side that are connected via the serial-data line and the serial-clock line, wherein the master device comprises a means for performing data communication with the slave devices via the serial-data line and the serial-clock line, and each of the slave devices comprises a means for performing data communication with the master device via the serial-data line and the serial-clock line, a means for comparing address information transmitted from the master device and inherent address specific to the slave device, a means for comparing the address information and a common address preset in a plurality of the slave devices, a means for outputting an acknowledge signal when the inherent address is specified as the address information, and a means for outputting an acknowledge signal when the common address is specified as the address information; and a means for outputting the acknowledge signal with combination of logics which are outputted from a plurality of the slave devices, each having the common address, to the serial-data line when the common address is specified.
According to the present invention, there is provided a serial-data transfer system for connecting at least one master device on a controlling side and a plurality of slave devices on a controlled side via a serial-data line for transferring data and a serial-clock line for transferring clock signals which control the data transfer, transmitting address information as one item of the data from the master device to the slave devices to specify a predetermined one of the slave devices, performing serial transfer of the data between the master device and the predetermined one of the slave devices which has been specified using the address information, and transferring an acknowledge signal from the specifie
Gaffin Jeffrey
Kawasaki Microelectronics Inc.
Schneider Joshua D
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