Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1999-02-12
2001-01-30
Thai, Xuan M. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S120000, C710S120000, C710S061000, C710S105000, C709S230000
Reexamination Certificate
active
06182175
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the area of serial digital data transmissions. It relates more particularly to a synchronous bus and its master/slave transmission protocol between a main processing unit (master) and a peripheral unit (slave).
An example of such a bus, used in different categories of equipment, is the so-called I
2
C bus described in European patent 0 051 332. A certain number of clock cycles are required for the microprocessor or microcontroller constituting the main processing unit to retrieve one byte of data (58 clock cycles in the case of the circuit marketed by the PHILIPS company with the reference number PCD 3316 which employs such a bus).
An object of the present invention is to propose a new synchronous serial bus protocol enabling faster access to certain data in the peripheral unit.
SUMMARY OF THE INVENTION
The invention thus proposes a process for serial data transfer between a main processing unit and a peripheral unit connected to each other by a bus including a data line and a clock line,
wherein the main processing unit controls synchronised transfer cycles by means of the clock line, including transfer cycles with addressing and direct transfer cycles,
wherein, during each cycle, the main processing unit transmits on the data line a strobe pulse while the clock line is at a first logic level,
wherein, before transmitting the strobe pulse in a transfer cycle with addressing, the main processing unit transmits on the data line bits of a transfer address, with corresponding synchronisation pulses on the clock line,
wherein, after receiving the strobe pulse in a transfer cycle with addressing, the peripheral unit accesses to a memory location determined from the transfer address to write or read data bits successively presented on the data line synchronously with corresponding synchronisation pulses on the clock line,
and wherein, after receiving the strobe pulse in a direct transfer cycle, the peripheral unit accesses to a memory location determined prior to said direct transfer cycle to write or read data bits successively presented on the data line synchronously with corresponding synchronisation pulses on the clock line.
The transfer protocol is very simple, thus enabling fast access. It is based on the detection of the strobe pulse on the data line by the peripheral unit. The main processing unit distinguishes between the different transfer modes through the position of this strobe pulse during the cycle, and/or by means of selection bits provided on the data line before the strobe pulse and/or by a decoding of the address bits.
Very fast access to some storage locations in the peripheral unit is made possible by the direct transfer mode, given that the main processing unit provides no address bits in this mode, and that the desired data is previously selected.
The location where the transmitted data bits are obtained in direct transfer mode may be a predetermined fixed location, which enables the structure of the bus interface of the peripheral unit to be simplified to the maximum and therefore its cost to be minimised.
It may also be a location whose address is obtained from data supplied by the main processing unit during a previous write cycle. In this case, direct read cycles can be run by the main processing unit to read different types of data in the peripheral unit. The number of bits read in this way may also be a parameter set by the main processing unit during a previous write cycle.
The direct read mode may particularly be used in the fast handling of some interrupts by the main processing unit.
Another advantage of the proposed bus is that it may share its data line and its clock line with those of a bus operating in accordance with another protocol for the exchange of data between the main processing unit and other entities.
According to another aspect, the present invention proposes a synchronous serial bus interface for a peripheral unit controlled by a main processing unit by means of a bus including a data line and a clock line including:
strobe pulse detection means, to detect strobe pulses occurring on the data line of the bus, while the clock line of the bus is at a first logic level;
a first shift register timed by the clock line of the bus, having a serial data input connected to the data line;
a second shift register having a serial data input connected to the serial data output of the first shift register or to the data line, and timed by the
output of an EXCLUSIVE OR gate having an input connected to the clock line of the bus, and another input receiving a binary selection signal;
an output switch connected on the one hand to the serial data output of the second shift register and on the other hand to the data line of the bus;
transfer cycle identification means, in order to analyse the content of the first shift register when a strobe pulse is detected so as to identify each transfer cycle to which a detected strobe pulse belongs;
write registers addressable from a write address obtained from the first shift register when a write cycle with addressing has been identified, a write cycle with addressing wherein the binary selection signal is held at 0, the output switch is kept open and the detection of the strobe pulse is followed by the parallel transfer of the content of the second shift register into the write register denoted by the write address;
read registers addressable from a read address when a read cycle has been identified, a read cycle wherein the detection of the strobe pulse is followed by the parallel transfer of at least part of the content of the read register denoted by the read address into the second shift register and by the serial transfer of the content of the second shift register to the output switch, a serial transfer during which the binary selection signal is set at 1 and the output switch is closed; and
transfer cycle managing means to obtain the read address from the first shift register when a read cycle with addressing has been identified, and to supply a previously specified read address when a direct read cycle has been identified.
REFERENCES:
patent: 4683530 (1987-07-01), Quatse
patent: 5434862 (1995-07-01), Lokhoff
patent: 5671421 (1997-09-01), Kardach et al.
patent: 5758073 (1998-05-01), Liang et al.
patent: 5928345 (1999-07-01), Tetzlaff et al.
patent: 0 051 332 B1 (1982-05-01), None
patent: 0 159 941 A2 (1985-10-01), None
patent: 0 498 494 A1 (1992-08-01), None
French Search Report dated Nov. 27, 1998.
Kilpatrick & Stockton LLP
Marcou George T.
Matra Nortel Communications
Thai Xuan M.
LandOfFree
Serial data transfer process, and synchronous serial bus... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Serial data transfer process, and synchronous serial bus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Serial data transfer process, and synchronous serial bus... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2483790