Serial data transfer device

Details Serial data transfer device Serial data transfer device

1998-08-04

2001-07-24

Etienne, Ario (Department: 2155)

Electrical computers and digital data processing systems: input/

Input/output data processing

C710S058000, C710S060000, C710S061000, C710S071000

Reexamination Certificate

active

06266710

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a data transfer device for unidirectional serial data transfer from a transmitting device to a receiving device, in particular from a microcontroller to an output stage IC of a motor vehicle control unit.
BACKGROUND INFORMATION
Serial data transfer has the significant advantage over parallel data transfer that fewer connecting lines are needed. In parallel data transfer, one transmission channel is needed for each bit of a data word to be sent, but with serial data transfer, all the bits of a data word are transmitted over the same transmission channel. This advantage is important in particular in data transfer over great distances. In general, serial transfer is used even for short distances if the reduced information transfer rate in comparison with parallel data transfer does not cause trouble.
In principle, in serial data transfer, the data word to be transmitted is shifted bit by bit on the transmitting end and is transmitted bitwise over the transmission channel and reconstructed by appropriate shifting on the receiver end. The transmission channel in this context is an electrical, optical or wireless, e.g., radio, connection for transfer of information.
A central difficulty in serial data transfer is synchronization between the transmitter and the receiver. The serial bit sequence is usually subdivided into individual blocks (transfer frames). In synchronous transfer, a certain bit sequence (synchronizing word) which cannot occur otherwise is inserted for synchronization. In this way, the receiver can recognize the beginning of a data block. In asynchronous transfer, the transmitting and receiving cycles are not synchronized, but instead they are set only approximately (about 3%) at the same frequency, and for each data burst a start signal and a stop signal are transmitted over the transmission channel as synchronizing signals. Therefore, only short data blocks can be transmitted between two synchronizing signals in asynchronous transfer.
In the related art, there are several different known serial interface formats for exchanging data between integrated components, e.g., the I
2
C bus (inter-integrated circuit bus) from IBM, the SPI interface (serial peripheral interface) and the SIOP port (simple serial I/O port) from Motorola.
The I
2
C bus has low transfer rates, namely less than 100 kbit/s. The maximum load on the bus is limited by the maximum bus capacity of 400 pF.
The SPI interface is usually operated asynchronously, and can be used only for short distances at a maximum of 4 Mbit/s.
The SIOP port is merely a slightly simplified form of SPI interface, but it operates according to the same principle.
Although it can be applied to any data transfer devices and interface devices, the present invention and the object on which it is based are explained in greater detail below with respect to serial data transfer from a microcontroller to an output stage IC (IC=integrated circuit), in particular of an automotive control unit.
FIG. 6
shows a conventional parallel control of an output stage IC by a microcontroller with an additional serial SPI diagnostic interface.
In
FIG. 6
, a transmitting device
10
is in the form of a microcontroller, and a receiving device
20
is in the form of an output stage IC to be driven by that microcontroller in parallel. The microcontroller has eight parallel output ports P
0
to P
7
connected to corresponding data lines D
0
-D
7
. At the other end, output stage IC has eight corresponding data inputs E
0
to E
7
, which are connected to corresponding data lines D
0
-D
7
. For example, data inputs E
0
to E
7
are each connected to a gate of a corresponding driver (indicated schematically).
A separate bidirectional serial interface
25
, e.g., in the form of a conventional SPI interface, is provided for diagnostic purposes; it is subject to much lower demands with regard to information transfer rate but must work in the duplex mode.
The control concept used so far and illustrated in
FIG. 6
thus calls for 8-bit point-to-point parallel coupling via data lines D
0
-D
7
. Owing to the increasing integration of functions in one microcontroller, there is necessarily also an increase in number of required data lines and pins. This has a negative effect on costs and operating reliability.
FIG. 7
shows the starting point for serial control of an output stage IC by a microcontroller according to the present invention.
Identical components or components having the same function in
FIG. 7
are labeled with the same reference numbers as those in FIG.
6
. In addition, microcontroller
10
has a conventional parallel-to-serial converter
12
which is connected at its parallel input end to data lines D
0
′ to D
7
′. A serial transfer line DS is connected at one end to the serial output end of parallel-to-serial converter
12
. At the other end, output stage
20
also has a conventional serial-parallel converter
22
which is connected at its serial input end to transfer line DS and at its parallel output end to data lines D
0
″ through D
7
″. Data lines D
0
″ through D
7
″ are connected to corresponding data inputs E
0
through E
7
of output stage IC
20
.
Thus, with this concept, the data and control signals are transmitted serially over single data line DS.
Serial data transfer to the output stage control reduces the number of pins on the transmitting microcontroller and on receiving output stage IC, and thus the associated enclosure costs. A lower number of pins makes the device even more fail-safe due to reduced contacting faults in IC manufacture and circuitboard assembly. A simpler and less expensive manufacturing process can thus be used for handling the corresponding components.
The disadvantages to be eliminated by the present invention include the fact that the usual synchronous serial data transfer devices are slow and/or they have a complicated design due to address parts contained in the transfer frame, for example. For analysis of conventional asynchronous serial interfaces, oversampling is always required, thereby reducing the maximum transfer rate by a multiple in comparison with the synchronous interface protocol described above.
SUMMARY OF THE INVENTION
The data transfer device according to the present invention is advantageous in that it has a high transfer rate for resolution of time-critical actuators such as injection valves, ignition, etc. It can achieve transfer rates (baud rates) up to almost the level of the available system clock.
Since there is no multiple assignment on the receiving end, no address part is necessary in the transfer frame either, thus simplifying the hardware expense for generation/analysis of the transfer frames. No duplex mode is necessary either, because the transmitting device and the receiving device do not communicate bidirectionally with one another over the channel according to the present invention.
Due to this seamless operation, no complicated handshake device is necessary, where possible errors are recognized and easily eliminated by a following data word. In general, faulty transfers can be stored on the receiving end for analysis and displayed by a status flag or IC pin or a conventional diagnostic interface.
According to the present invention, the respective conversion operations of the P/S and S/P converters are performed continuously by, and in-phase with, the clock signal and are synchronized by the synchronizing signal according to the conversion operation of the P/S converter.
According to another embodiment, the P/S converter has an input register clocked with the clock signal for receiving the parallel data stream at a parallel input and for outputting a corresponding parallel output signal at a parallel output; a first shift register clocked with the clock signal, with a parallel input for receiving the parallel output signal and with a serial output for outputting the serial data stream to the data transfer channel; and a first internal bus for connecting the output of the input r

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