Static information storage and retrieval – Read/write circuit – Sipo/piso
Patent
1994-06-28
1995-05-02
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Sipo/piso
365221, 36518907, G11C 700
Patent
active
054126100
ABSTRACT:
A serial data transfer device has a FIFO memory for storing plural parallel data, a status register for indicating the actual number of residual data in the FIFO memory, a set register for arbitrarily setting the number of residual data in the FIFO memory, and a comparison circuit for comparing the indication value of the status register with the value of the set register. The indication value of the status register which indicates the actual number of residual transmit data (or residual receive data) in the FIFO memory is compared with the value of the set register in which a specific number of residual transmit data (or residual receive data) in the FIFO memory is set. Only when the number of residual transmit data (or residual receive data) in the FIFO memory is decreased (or increased) to the predetermined number of data, an interrupt signal is issued to a CPU.
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patent: 5255238 (1993-10-01), Ichige et al.
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WEITEK XL-8220 Processor Data Book, Preliminary Data, Mar. 1990.
Motorola User's Manual Integrated Processor MC68332, Oct. 1991, pp. 120-121.
"M66230P/FP, A.sup.2 RT (Advanced Asynchronous Reciever & Transmitter)" Mitsubishi Simiconductor Circuit <Digital ASSP> May 1989, pp. 2-35.about.2-47.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tan
Popek Joseph A.
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