Serial data transfer apparatus

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

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Details

395872, G06F 1200

Patent

active

058025952

ABSTRACT:
The invention provides a serial data transfer apparatus wherein communication management for serial communication data of a low rate can be executed without an increase in hardware or software scale and such communication management and event management of communication data can be selectively executed. The serial data transfer apparatus includes a control circuit which in turn includes a latch circuit which generates a write control signal to write, each time one communication is completed, a time base count value into a storage region of a reception buffer corresponding to input data. The serial data transfer apparatus further includes a multiplexer which selects, in response to a mode signal supplied thereto, one of a first clock signal and a second clock signal corresponding to the write control signal and supplies the selected clock signal as a count clock signal to a time base counter.

REFERENCES:
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patent: 4952367 (1990-08-01), Porter
patent: 5530901 (1996-06-01), Nitta
patent: 5559994 (1996-09-01), Ando
patent: 5566343 (1996-10-01), Nishiguchi
patent: 5644787 (1997-07-01), Nakamura

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