Serial data communication interface architecture

Details Serial data communication interface architecture Serial data communication interface architecture

1993-06-22

1994-11-22

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

341100, H03M 900

Patent

active

053673000

ABSTRACT:
A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with a successive approximation registers signal (SARS). Once the internal data conversion begins, the chip select signal may change to any signal state without interrupting the conversion process. Serial interface data output and SARS lines are tri-stated during conversion, while the chip select signal is high. This allows data input, data output, and SARS lines to serve other purposes during conversion. If chip select signal is high at the falling edge of SARS, converted data DO bits are then provided to an internal output register. However, DO data are not immediately routed to the output. Clocking of the output data does not resume until at the first transition to low of chip select signal after the falling edge of SARS. The next conversion is not initiated until the second transition of chip select back to low after the falling edge of SARS signaling the end of conversion.

REFERENCES:
patent: 4652874 (1987-03-01), Loyer
National Semiconductor Paper "ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer".

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