Serial data-and control-bus with distribution voltage

Details Serial data-and control-bus with distribution voltage Serial data-and control-bus with distribution voltage

1999-09-22

2002-07-23

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S106000

Reexamination Certificate

active

06425030

ABSTRACT:

The present invention relates to a bus system for the transmission of digital test data or control commands. Several such bus systems are known and differentiate themselves from each other by the type of transmission, the addressing, the number of conductors and the energy transmitted.
A large major group of bus systems are concerned with the parallel transmission of data. They are not considered further here, since they are not relevant with regard to the present invention. The second large major group works with serial transmission of the data and represents the state of the technology.
In the narrow sense, the state of the technology is formed from systems in which a multiplicity of participants of an active or passive nature (so-called Bus-Transceivers, BT) are connected to the actual data bus.
Such bus systems are known, for instance, from EP 0 146 045 A2 (henceforth D
1
), U.S. Pat. No. 4,497,391 (henceforth D
2
), EP 0 540 449 A1 (henceforth D
3
) and EP 0 728 621 A2 (henceforth D
4
).
D
1
describes a carrier frequency system in which a normal electronic supply conductor is used as the data bus. In D
2
, a lift control is described that connects on one side the stationary selector stations, on the other the selector station in the lift via two four-wire systems—in the sense of the definition chosen here of all Bus Transceivers (BT)—with the actual lift controller or main station. The addressing is effected by means of a time slot system, wherein each BT is allocated a certain time-defined address twice in each address cycle, the first time for the transmission of signals from BT to the main station and the second time for the reverse direction.
From D
3
, a fast data connection system is known essentially for application in and by computer systems. The system of D
3
is especially optimised for high transmission speeds. The data transmission of each BT is effected separated in time according to sending and receiving; even so, a multiplicity of conductors are provided for the data bus.
The multiplicity of conductors are always brought together in pairs for the formation of a differential signal.
Further, a bus system developed for application in motor vehicles is known from D
4
. The bus system of D
3
has a data transmission based on pulse height selection, whereby the transmitted information is encoded using pulse width modulation and has a higher voltage level than the supply voltage of the single wire bus system. The zero reference voltage is essentially the potential of the vehicle chassis as the return conductor to the battery. A further feature in accordance with the invention is the trapezoidal type current pulse shape for the reduction of discontinuous transitions.
Each of the four systems listed here as examples has its own characteristics and is designed for special applications. The use of one system in the typical application area of another generally leads to great difficulties. Further, in all the documents quoted, systems are presented, which—including the power supply—require at least three conductors and in all cases have BT installed by specialists (which nonetheless does not exclude installation faults; see D
2
).
An aim addressed by the present invention is provision of a bus system for serial transmission of digital data with a multiplicity of single addressable BTs. The multiplicity of single addressable BTs are connected by only one two wire common bus. The one two wire common bus can provide the energy supply of the BTs as well as the users connected to them at any time. It is possible with the one two wire common busto transmit from precisely one transmitting BT simultaneously to two or more receiving BTs and to transmit the result of a logical element operation, that is the current logical sum (OR Gate) or the current logical product (AND Gate), of the digital data from two or more simultaneously transmitting BTs, simultaneously to one or more or even several receiving BTs at the same time. This bus system can thereby be set into operation and operated without the use of software and additionally can be designed such that polarity errors are excluded.


REFERENCES:
patent: 4357605 (1982-11-01), Clements
patent: 4497391 (1985-02-01), Mendelsohn et al.
patent: 4558316 (1985-12-01), Yong
patent: 4583091 (1986-04-01), Sugiura et al.
patent: 4770842 (1988-09-01), Kelly et al.
patent: 5182745 (1993-01-01), Heichler
patent: 5696777 (1997-12-01), Hofsaess
patent: 0146045 (1985-06-01), None
patent: 0540449 (1993-05-01), None
patent: 0728621 (1996-08-01), None
International Search Report,Jan. 29, 1999, 2 pgs.

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