Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-03-08
2011-03-08
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S784000, C714S786000
Reexamination Certificate
active
07904784
ABSTRACT:
A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder includes an input buffer memory one or more processing loop modules, and an output buffer memory. Each processing loop module includes a permutation module, inner decoding engines, a depermutation module, and outer decoding engines. The depermutation module includes a concatenating device and two or more depermutation buffer memories. The concatenating device is configured for writing a codeword segment containing a plurality of soft-decision bits to each of the depermutation buffer memories in a single write operation. The permutation module also includes a concatenating device and two or more permutation buffer memories. The concatenating device is configured for writing a codeword segment containing a plurality of soft-decision bits to each of the depermutation buffer memories in a single write operation.
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Cobb Matthew C.
Dyson Timothy F.
Laprade Maria
Abraham Esaw T
Fox Rothschild LLP
Harris Corporation
Sacco Robert J.
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