Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1990-11-30
1993-04-27
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523008, 371 103, G11C 1134, G06F 1120
Patent
active
052068315
ABSTRACT:
A serial access semiconductor memory device having a column redundant system employs a parallel-serial conversion circuit including a plurality of series connected flipflop circuits and a plurality of selectors provided between the flipflop circuit. At the selector associated unit the final stage of the flipflop circuits in the parallel-serial conversion circuit, defective data from a memory cell array are replaced to redundant data from the column redundant system without large scale circuitry and complicated control signals. An improved fuse ROM or an improved comparator is employed for the semiconductor memory device to control the switching from the defective data to redundant data. The fuse ROM employs a latch circuit for reducing stand-by current. The comparator employs a plurality of MOS transistors to compare effectively. The relation between the fuse ROM and the comparator provides a simplified circuit construction of an asynchronous multi-port device or a device having a plurality of memory blocks.
REFERENCES:
patent: 4701887 (1987-10-01), Ogawa
Popek Joseph A.
Sony Corporation
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