Serial access semiconductor memory device and operating method t

Details Serial access semiconductor memory device and operating method t Serial access semiconductor memory device and operating method t

1991-07-08

1993-04-06

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Sipo/piso

36518912, 36523003, 365239, 365240, 340799, 340800, 340802, G11C 700, G11C 804

Patent

active

052009254

ABSTRACT:
A serially accessible memory device includes a plurality of memory cell array blocks, a plurality of input buffers each separately provided for each cell array block for receiving different data in a data stream, a plurality of output buffers each separately provided for each memory cell array block, and a plurality of registers each separately provided for each memory cell array block for effectuating data transfer collectively to and from corresponding memory cell array blocks at the same time. All of the registers shift data received from corresponding input buffer to latch the data therein in response to a single clock signal in a data writing operation and also shift latched data received from corresponding array block to provide the data to corresponding output buffer in response to another single clock signal in data reading operation. Both the shifting clock signals are derived from an external clock defining the device operation rate.

REFERENCES:
patent: 4633441 (1986-12-01), Ishimoto
patent: 4683555 (1987-07-01), Pinkham
patent: 4855959 (1989-08-01), Kobayashi
patent: 4943947 (1990-07-01), Kobayashi
Pinkham et al., "A 128K x 8 70 MHz Video RAM with Auto Register Reload," IEEE International Circuits Conference, Feb. 19, 1988, pp. 236 and 237.
Weste et al., Principles of CMOS VLSI Design: A Systems Perspective, 1985 (AT&T Bell), Ch. 5.4.5, pp. 212-215.
Stout et al., Handbook of Microcircuit Design and Application, 1986 (McGraw Hill), Ch. 4, pp. 4-12, & 4-13.

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