Serial access memory system provided with improved cascade buffe

Details Serial access memory system provided with improved cascade buffe Serial access memory system provided with improved cascade buffe

1989-02-06

1990-05-01

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

36518903, 36518905, 365221, 365233, 365 73, G11C 700, G11C 1142

Patent

active

049224573

ABSTRACT:
A serial access memory device with the improved cascade buffer circuit for controlling serial access operation which has a small number of external terminals is disclosed. The cascade buffer circuit includes first and second external terminals, a first control circuit for enabling the memory device to perform write operation and read operation when the level at the first external terminal rises or falls and when the level at the first external terminal falls or rises, respectively and a second control circuit for operatively causing the second external terminal to rise or fall when the memory device completes write operation and causing the second external terminal to fall or rise when the memory device completes read operation, respectively.

REFERENCES:
patent: 4222102 (1980-09-01), Jansen et al.
patent: 4779234 (1988-10-01), Kaneko et al.
patent: 4825415 (1989-04-01), Nakaizumi
patent: 4829471 (1989-05-01), Banerjee et al.
patent: 4829475 (1989-05-01), Ward et al.
patent: 4833655 (1989-05-01), Wolf et al.

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