Static information storage and retrieval – Read/write circuit – Serial read/write
Reexamination Certificate
2002-12-02
2004-04-27
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Serial read/write
C365S189120, C365S239000
Reexamination Certificate
active
06728155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a serial access memory and a data write/read method applicable thereto.
2. Prior Art
Generally, in a serial access memory of the line access type, when a line address (X-address) is externally applied thereto, the access (i.e. write/read operation) is executed to a word line as specified with that line address. An exemplary arrangement of a prior art serial access memory
1
of the line access type is illustrated in
FIG. 11
of the accompanying drawings as a part of this specification.
The prior art serial access memory
1
is provided with a memory cell array
11
, a memory control portion
12
, an X-address means
13
, a Y-address means on the write side (referred to “write Y-address means” hereinafter)
14
, a Y-address means on the read side (referred to “read Y-address means)
15
, the first transfer means group on the write side (referred to as “write side first transfer means group” hereinafter)
16
, a register group on the write side (referred to as “write register group” hereinafter)
17
, the second transfer means group on the write side (referred to as “write side second transfer means group” hereinafter)
18
, the first transfer means group on the read side (referred to “read side second transfer means group)
19
, a register group on the read side (referred to as “read register group”)
20
, the second transfer means group on the read side (referred to as “read side second transfer means group” hereinafter)
21
, an input means
22
, and an output means
23
.
The X-address means
13
is controlled to select one word line from a plurality of word lines WL
1
to WLn (n: positive integer) and to put the selected word line in a logical high-level state (referred to as “H-level” hereinafter) by the memory control portion
12
.
The memory cell array
11
is made up of a plurality of memory cells MC
11
to MCmn (m: positive integer), each of which is arranged at each of intersections made by the plural word lines WL
1
to WLn and the plural bit line pairs BL
1
, /BL
1
to BLm, /BLm. Each of the memory cells MC
11
to MCmn includes one each of a transistor (not shown) and a capacitor (not shown).
The bit line pairs BL
1
, /BL
1
to BLm, /BLm are respectively connected with corresponding sense amplifiers SA
1
to SAm, with which the potential variation appearing on the bit line pairs BL
1
, /BL
1
to BLm, /BLm is amplified.
In the next, there will be describe the structure of an electronic circuit arranged on the write side of the memory cell array
11
.
The bit line pairs BL
1
, /BL
1
to BLm, /BLm are connected with the write register group
17
through the write side first transfer means group
16
. The write side first transfer means group
16
is made up of a plurality of write side first transfer means
16
-
1
to
16
-
m
of which each corresponds to each of the bit line pairs BL
1
, /BL
1
to BLm, /BLm. The write register group
17
is made up of a plurality of write registers Wreg-
1
to Wreg-m of which each corresponds to each of the bit line pairs BL
1
, /BL
1
to BLm, /BLm.
Each of the write side first transfer means
16
-
1
to
16
-
m
is made up of two transistors. For instance, the bit line BL
1
is connected with the write register Wreg-
1
through the drain and source of one transistor forming the write side first transfer means
16
-
1
while the bit line /BL
1
is connected with the write register Wreg-
1
through the drain and source of the another transistor forming the write side first transfer means
16
-
1
. The ON/OFF control of these 2×m transistors forming the write side first transfer means
16
-
1
to
16
-
m
is carried out with a control signal WT.
The write register group
17
is connected with write data buses WD, /WD through the write side second transfer means group
18
. This write side second transfer means group
18
is made up of a plurality of write side second transfer means
18
-
1
to
18
-
m
, which correspond to the write registers Wreg-
1
to Wreg-m making up the write register group
17
, respectively.
Each of the write side second transfer means
18
-
1
to
18
-
m
is made up of two transistors. For instance, the write register Wreg-
1
is connected with write data buses WD, /WD through respective drains and sources of two transistors forming the write side second transfer means
18
-
1
. Each of the write side second transfer means
18
-
1
to
18
-
m
is made up so as to receive the write Y-address signals YW
1
to YWm outputted from the write Y-address means
14
, and the ON/OFF control of two transistors forming each of the write side second transfer means
18
-
1
to
18
-
m
is carried out with the write Y-address signals YW
1
to YWm.
The write data buses WD, /WD are connected with an input terminal DIN through the input means
22
.
In the next, there will be described the structure of an electronic circuit arranged on the read side of the memory cell array
11
.
The bit line pairs BL
1
, /BL
1
to BLm, /BLm are connected with the read register group
20
through the read side first transfer means group
19
. The read side first transfer means group
19
is made up of a plurality of read side first transfer means
19
-
1
to
19
-
m
, of which each corresponds to each of the bit line pairs BL
1
, /BL
1
to BLm, /BLm. The read register group
20
is made up of a plurality of read registers Rreg-
1
to Rreg-m, of which each corresponds to each of the bit line pairs BL
1
, /BL
1
to BLm, /BLm.
Each of the read side first transfer means
19
-
1
to
19
-
m
is composed of two transistors. For instance, the bit line BL
1
is connected with the read register Rreg-
1
through the drain and source of one transistor forming the read side first transfer means
19
-
1
while the bit line /BL
1
is connected with the read register Rreg-
1
through the drain and source of the another transistor forming the read side first transfer means
19
-
1
. The ON/OFF control of these 2×m transistors forming the read side first transfer means
19
-
1
to
19
-
m
is carried out with a control signal RT.
The read register group
20
is connected with read data buses RD, /RD through the read side second transfer means group
21
. This read side second transfer means group
21
is composed of a plurality of read side second transfer means
21
-
1
to
21
-
m
respectively corresponding to the read registers Rreg-
1
to Rreg-m which make up the read register group
20
.
Each of the read side second transfer means
21
-
1
to
21
-
m
is made up of two transistors. For instance, the read register Rreg-
1
is connected with read data buses RD, /RD through the respective drains and sources of two transistors forming the read side second transfer means
21
-
1
. Each of the read side second transfer means
21
-
1
to
21
-
m
is formed so as to receive the read Y-address signals YR
1
to YRm outputted from the read Y-address means
15
, and the ON/OFF control of two transistors forming each of the read side second transfer means
21
-
1
to
21
-
m
is carried out with the read Y-address signals YR
1
to YRm.
The read data buses RD, /RD are connected with an output terminal DOUT through an output means
23
.
The write/read operation of the prior art serial access memory
1
as arranged above will now be described with reference to FIGS.
12
and
13
.
FIG. 12
is a timing chart for describing the write operation of the serial access memory
1
. The write operation will be described with the passage of time as shown in the figure.
<Time t
1
> The write operation is commenced when a write X-address WXAD is serially inputted to the memory control portion
12
. At this stage, however, in order to make it possible for the memory control portion
12
to take in the write X-address WXAD, a write address enable signal WADE of the H-level is inputted in advance to the memory control portion
12
. To begin with, at time t
1
, the most significant bit (MSB) data Am of the write X-address WXAD is taken in the memory control portion
12
. After that, each
Hoang Huan
Oki Electric Industry Co. Ltd.
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