Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1993-04-19
1995-03-28
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 53, 326 21, H03K 19096
Patent
active
054020123
ABSTRACT:
The present invention relates to an implementation of domino logic using a logic cell which is not limited to the use of positive logic functions, and which can be implemented using MOS technology. A significant feature of the present invention relates to use of a single clock cycle to generate separate clock phases for a first function (e.g., carry function of a full-adder logic cell) and a second function (e.g., sum function in the full-adder logic cell). The separate clock phase used to gate the second function corresponds to a delayed version of the clock phase used to gate the first function, wherein the clock delay corresponds to a delay through the first function. In one exemplary embodiment, the delay can be made equal to that of the first function by using circuitry identical to that of the first function to create the delay period.
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Lu, Fang and Henry Samueli; "A 200-MHz CMOS Pipelined Multiplier-Accumulator Using a Quasi-Domino Dynamic Full-Adder Cell Design"; IEEE of Solid-State Circuits, vol. 28, No. 2, Feb. 1993; pp. 123-132.
Excerpts from Chapter 6 of a textbook entitled The Design and Analysis of VLSI Circuits, Lance A. Glasser et al, 1985, which relate to a section entitled "Domino and Rippling Logic", including FIGS. 6.16 to 6.19 (6 pages).
Hudspeth David R.
VLSI Technology Inc.
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