Sequential nibble burst ordering for data

Details Sequential nibble burst ordering for data Sequential nibble burst ordering for data

2001-12-07

2004-08-10

Gossage, Glenn (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S105000, C365S230030, C365S233100, C365S238500

Reexamination Certificate

active

06775759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to memory devices and, more particularly, to methods and circuits for reading information into and out of a memory device.
2. Description of the Background
Computer designers are continually searching for faster memory devices that will permit the design of faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory devices such as dynamic random access memories (DRAMs), synchronous dynamic random access memories (SDRAMs), flash memories, etc. typically include a large number of memory cells arranged in one or more arrays, each array comprised of rows and columns. Each memory cell provides a location at which the processor can store and retrieve one bit of data, sometimes referred to as a memory bit or m-bit. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1
shows, in part, a typical computer system architecture. A central processing unit (CPU) or processor
10
is connected to a processor bus
12
, which in turn is connected to a system or memory controller
14
. The memory controller
14
may be connected to an expansion bus
16
. The memory controller
14
serves as interface circuitry between the processor
10
and a memory device
18
. The processor
10
issues a command and an address which are received and translated by the memory controller
14
. The memory controller
14
applies the translated command signals on a plurality of command lines
20
and the translated address on a plurality of address lines
22
to the memory device
18
. These command signals are well known in the art and include, in the case of a DRAM, RAS (row address strobe), CAS (column address strobe), WE (write enable) and OE (output enable), among others. A clock signal is also provided on CLK lines
24
. Corresponding to the processor-issued command and address, data is transferred between the controller
14
and the memory
18
via datapath lines
26
.
Methods exist to enable memory devices, such as DRAM memory
18
, to appear to external devices to be operating faster than the time it takes for the memory device to retrieve data from the array. These methods include pipeline and prefetch methods of operation. The pipeline method divides internal processing into a number of stages and sequentially processes information relating to one unit of data through each stage. Processing in each stage is carried out simultaneously in parallel, such that the rate at which data can be output from the device can be greater than the rate at which data is retrieved from the array. In the prefetch method, all internal processing is carried out in parallel, and parallel to serial conversion is performed at the input/output section.
Both the pipeline and prefetch methods can be used to support, for example, a burst mode of operation. The burst mode of operation is a mode of operation in which the starting address for a data string is provided to the memory device. The data string to be read out of the memory or written into the memory is then synchronously output or input, respectively, with a clock signal.
Historically, synchronous DRAMs have supported both an interleaved and a sequential burst mode of operation. Advance DRAM technology standards are being defined with an 8-bit external prefetch and capability to support a 4-bit or 8-bit internal prefetch. With a 4-bit internal prefetch, the sequential read or write crosses a boundary and is therefore difficult to implement as illustrated by the following table, Table 1.
TABLE 1
Starting
Internal Bits
Internal Bits
Address
[0 1 2 3]
[4 5 6 7]
0
0 1 2 3
4 5 6 7
1
1 2 3 4
5 6 7 0
2
2 3 4 5
6 7 0 1
3
3 4 5 6
7 0 1 2
4
4 5 6 7
0 1 2 3
5
5 6 7 0
1 2 3 4
6
6 7 0 1
2 3 4 5
7
7 0 1 2
3 4 5 6
As seen from Table 1, except for starting addresses
0
and
4
, the sequential burst cannot be executed without an 8-bit internal burst, adding cost, or a dual prefetching, which adds latency.
The existing interleave burst mode supports a 4-bit internal prefetch but some applications still use a sequential type of access burst mode. One solution is to always start the read burst at index
0
and sequence through the data. That solution is acceptable only when the word stored at index
0
is the next critical word. If the critical word is indexed at any other location, latency is introduced.
Thus, the need exists for a method and apparatus for enabling both 8-bit and 4-bit internal prefetches for new architectures without adding cost or latency to the new architecture.
SUMMARY OF THE INVENTION
The present invention is directed to a memory device comprising a plurality of arrays of memory cells and peripheral devices for reading information out of and for writing information into the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may be a read address or a write address, and the order may be the order for reading data or writing data, respectively.
The present invention also includes a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be written to or read from, as the case may be, the memory in response to another portion of the address information. The necessary address information is routed to the sequencer circuits by an address sequencer.
The present invention is also directed to a method of reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit, or writing a word in two n-bit bytes under the control of the address bit.
In one implementation of the present invention, the new burst sequence splits, for example, an 8-bit burst into two 4-bit bursts with a sequential interleave within each burst sequence. That enables each of the 4-bit bursts to be output from a memory array before the 8-bit burst is required to be output from the memory device. To implement that operation, the most significant column address bits (for example CA
3
-CAi) identify which 8-bit burst is selected. Those address bits may be referred to as a first portion of the address information. Address bit CA
2
, referred to as a second portion of the address information, identifies which of the two 4-bit bursts are fetched first from the memory array. CA
0
and CA
1
may then be used to identify which of the prefetched 4-bits are to be asserted first, with the remaining 3 bits output in sequential order from the first bit.
The present invention allows sequential type of interleaves for applications requiring them and provides access to the most critical word first without adding any latency to the system. Those, and other advantages and benefits, will become apparent from the detailed description of the preferred embodiments hereinbelow.


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