Sequential nibble burst ordering for data

Details Sequential nibble burst ordering for data Sequential nibble burst ordering for data

2008-03-04

2008-03-04

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S167000, C711S204000, C711S213000

Reexamination Certificate

active

07340584

ABSTRACT:
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address information for identifying an order in which one or more portions of the identified word are to be read or written. An address sequencer routes at least one bit of the address information. A sequencer circuit is responsive to the address sequencer for ordering the plurality of data bits within each portion of the identified word.

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