Sequential memory accessing circuit and method of addressing two

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

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711104, 711218, 711219, G06F 1202

Patent

active

059833114

ABSTRACT:
A sequential memory access circuit for access to various memory units is provided. The sequential memory access circuit is coupled between an external system and at least two memory units including a RAM unit and a ROM unit. The sequential memory access circuit includes a common data pointer circuit, responsive to a reset signal, a write request signal, and a read request signal from said external system, for generating accordingly a RAM enable signal, a ROM enable signal, and a counter signal, for control of the access to the RAM unit and the ROM unit. Further, a length register is used to generate a bound control signal to said common data pointer circuit in response to the write request signal and the counter signal. A sequential access dedicated comparator is used to provide the controls for the access to the two memory units. The structure of the sequential memory access circuit allows for a small circuit layout area and a reduced delay time.

REFERENCES:
patent: 4764895 (1988-08-01), Armstrong
patent: 5469566 (1995-11-01), Hohenstein et al.

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