Sequential logic circuit with active and sleep modes

Details Sequential logic circuit with active and sleep modes Sequential logic circuit with active and sleep modes

1999-10-04

2001-10-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S113000, C327S185000

Reexamination Certificate

active

06310491

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sequential logic circuit and more particularly, to a sequential logic circuit equipped with a latch circuit having active and sleep modes.
2. Description of the Prior Art
In recent years, semiconductor integrated logic devices have been designed to cope with both high-speed operation in the active mode and low power-dissipation in the sleep mode. The “active mode” is the state where the normal operation of the logic devices are performed. The “sleep mode” is the state where the normal operation of the logic devices are stopped. The “sleep mode” may be termed the “power-down mode” because of its purpose of reducing the power dissipation. It is important for the semiconductor integrated logic devices of this sort to prevent the stored information in the devices from being broken especially in the sleep mode.
An example of the prior-art semiconductor integrated logic devices of this sort is disclosed in the Japanese Non-Examined Patent Publication No. 7-271477 published in October 1995. This semiconductor integrated logic device, which is shown in
FIG. 15
of this Publication, is formed by Metal-oxide-semiconductor Field-Effect Transistors (MOSFETs) whose threshold voltage is low (i.e., low-threshold MOSFETs) and is operated at a low power supply voltage.
MOSFETs having the low threshold voltage have a characteristic that the subthreshold current (i.e., current leakage) flowing between the source and drain during the OFF state is comparatively large. Therefore, an upper-side power supply and a lower-side power supply are connected to the logic circuits through MOSFETs whose threshold voltage is high (i.e., high-threshold MOSFETs). This is because high-threshold MOSFETs have low current leakage during the OFF state. Moreover, a bistable circuit formed by high-threshold MOSFETs is added to the logic circuit. The bistable circuit is directly supplied with a power supply. Thus, the subthreshold leakage current is prevented in the sleep mode and at the same time, the information stored in the logic circuit is prevented from being broken or lost.
Furthermore, with the prior-art semiconductor integrated logic device, when the sleep mode is finished, the logic device is supplied with the upper- and lower-side power supplies again and then, the instruction for holding the clock signal is canceled. At the start of the sleep mode, the clock signal is shifted to its holding state and then, the logic circuit is shifted from the active mode to the sleep mode.
Next, the above-described prior-art semiconductor integrated logic device disclosed in the Japanese Non-Examined Patent Publication No. 7-271477 is explained in detail with reference to FIG.
1
.
As shown in
FIG. 1
, this prior-art logic circuit is comprised of a latch circuit FF
102
having set and reset functions. The latch circuit FF
102
includes two transmission gates TM
1
and TM
2
, three inverters INV
101
, INV
102
, and INV
103
, and a NOR gate NOR
101
.
The inverter INV
101
has a p-channel MOSFET having a low threshold voltage (i.e., low-threshold p-channel MOSFET) (not shown) and a low-threshold n-channel MOSFET (not shown). The gates of these two MOSFETs are coupled together to be connected to an input terminal of the inverter INV
101
to which a data signal D is applied. The drains of these two MOSFETs are coupled together to be connected to an output terminal of the inverter INV
101
from which an output signal D
1
is derived. The source of the p-channel MOSFET is connected to an upper-side power supply of V
DD
through a high-threshold p-channel control MOSFET HP
101
. The source of the n-channel MOSFET is connected to a lower-side power supply (i.e., the ground potential GND) through a high-threshold n-channel control MOSFET HN
101
. The output signal D
1
of the inverter INV
101
is applied to a bidirectional terminal of the transmission gate TM
101
. Thus, the inverter INV
101
is formed by the low-threshold MOSFETs and therefore, it is capable of high-speed operation.
The high-threshold MOSFET HP
101
serves to connect the inverter
101
to the upper-side power supply of V
DD
or disconnect the inverter
101
therefrom in response to a sleep mode signal SL. Similarly, the high-threshold MOSFET HN
101
serves to connect the inverter
101
to the ground GND or disconnect the inverter
101
therefrom in response to an inverted sleep mode signal SLB. The signal SLB has an inverted value to that of the signal SL.
To enter the sleep mode, the sleep mode signal SL is in the logic high (H) level (i.e., SL=1) and the inverted sleep mode signal SLB is in the logic low (L) level (i.e., SLB=0). At this stage, the control transistors HP
101
and HN
101
are turned off, blocking the supply of the supply voltage V
DD
and the ground potential GND to the inverter INV
101
. Since the control transistors HP
101
and HN
101
have the high threshold voltages, they have small subthreshold leakage currents, which decreases the power consumption in the sleep mode.
The transmission gate TM
101
has a low-threshold p-channel MOSFET (not shown) and a low-threshold n-channel MOSFET (not shown). The drain and source of the p-channel MOSFET are connected to the source and drain of the n-channel MOSFET, respectively. The gate of the n-channel MOSFET is applied with a clock signal &phgr;. The gate of the p-channel MOSFET is applied with an inverted clock signal *&phgr;. The signal *&phgr; has an inverted value to that of the signal &phgr;. One of the bidirectional terminals of the transmission gate TM
101
is connected to the output terminal of the inverter INV
101
and the other is connected to a second input terminal of the NOR gate NOR
101
.
As described above, the NOR gate NOR
101
is formed by the low-threshold MOSFETs and therefore, it is capable of high-speed operation.
The NOR gate NOR
101
has first and second low-threshold p-channel MOSFETs (not shown) and first and second low-threshold n-channel MOSFETs (not shown). The first and second -channel MOSFETs are connected in series to form two terminals, one of which is applied with the power supply voltage V
DD
and the other is connected to an output terminal of the NOR gate NOR
101
. The gate of the first p-channel MOSFET, which is connected to a first input terminal of the gate NOR
101
, is applied with a reset signal RT. The gate of the second p-channel MOSFET, which is connected to the second input terminal of the gate NOR
101
, is applied with the output signal D
2
from the transmission gate TM
101
. The first and second n-channel MOSFETs are connected in parallel to form two terminals, one of which is connected to the ground GND and the other is connected to the output terminal of the NOR gate NOR
101
. The gate of the first n-channel MOSFET, which is connected to the first input terminal of the gate NOR
101
, is applied with the reset signal RT. The gate of the second n-channel MOSFET, which is connected to the second input terminal of the gate NOR
101
, is applied with the output signal D
2
from the transmission gate TM
101
.
The output signal D
3
of the NOR gate NOR
101
, which is the result of the NOR operation between the signal D
2
and the reset signal RT, is outputted as an output signal Q from an output terminal of the latch circuit FF
102
to a next-stage circuitry (not shown). At the same time as this, the signal D
3
is further applied to the inverter INV
102
.
Since the NOR gate NOR
101
is formed by the low-threshold MOSFETs, it is capable of high-speed operation.
The NOR gate NOR
101
is supplied with the upper-side power supply of V
DD
through a high-threshold p-channel control MOSFET HP
102
and with the ground potential GND through a high-threshold n-channel control MOSFET HN
102
. The high-threshold MOSFET HP
102
serves to connect the gate NOR
101
to the power supply of V
DD
or disconnect the inverter
101
therefrom in response to the sleep mode signal SL. Similarly, the high-threshold MOSFET HN
102
serves to connect the gate NOR
101
to the ground GND

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