Sequential logic circuit for frequency division

Details Sequential logic circuit for frequency division Sequential logic circuit for frequency division

2005-02-15

2005-02-15

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S046000, C331S051000

Reexamination Certificate

active

06856172

ABSTRACT:
A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or both set and reset input ports of the set-reset flip-flop. The set-reset flip-flop and shift register are clocked by the clock signal. The output signal of the circuit may be taken at any output port of the shift register or the set-reset flip-flop. In one embodiment, the state of the shift register is represented by the set of Boolean values Q<i>, i=1, 2, . . . , N−1, and the combinational logic provides to the set input port of the set-reset flip-flop the Boolean value {Q#<M−1>img id="CUSTOM-CHARACTER-00001" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?<Q#<M−2>img id="CUSTOM-CHARACTER-00002" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?. . .img id="CUSTOM-CHARACTER-00003" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?Q#<0>}, where Q#<i>is the Boolean complement of Q<i>, Q#<0> is provided by the set-reset flip-flop,img id="CUSTOM-CHARACTER-00004" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?is Boolean AND, and M is a positive integer not greater than N; and the combinational logic also provides the Boolean value {Q<L−1>img id="CUSTOM-CHARACTER-00005" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?<Q<L−2>img id="CUSTOM-CHARACTER-00006" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?. . .img id="CUSTOM-CHARACTER-00007" he="2.46mm" wi="1.44mm" file="US06856172-20050215-P00900.TIF" alt="custom character" img-content="character" img-format="tif" ?Q<0>} to the reset input port of the set-reset flip-flop, where L is a positive integer not greater than N. For such an embodiment, the frequency of the output signal is that of the clock signal divided down by the divisor D where D L+M, and the duty cycle of the output signal is L/D.

REFERENCES:
patent: 4333374 (1982-06-01), Okumura et al.
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5123030 (1992-06-01), Kazawa et al.
patent: 6269051 (2001-07-01), Funaba et al.
patent: 6498537 (2002-12-01), Watanabe

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