Sequential equivalence checking for asynchronous verification

Details Sequential equivalence checking for asynchronous verification Sequential equivalence checking for asynchronous verification

2011-02-01

2011-02-01

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S093000, C326S094000, C326S095000, C326S096000, C327S001000, C327S002000, C327S003000, C327S040000, C327S041000, C703S013000, C703S014000, C703S015000, C703S016000, C703S019000

Reexamination Certificate

active

07882473

ABSTRACT:
Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.

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