Sequential data transfer with common clock signal for...

Details Sequential data transfer with common clock signal for... Sequential data transfer with common clock signal for...

2000-11-02

2002-03-19

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Flow controlling

C710S057000, C710S074000, C713S600000, C709S239000

Reexamination Certificate

active

06360286

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to data communications within a computer. In particular, the present invention relates to the use of a slack register for time critical data flow control.
BACKGROUND OF THE INVENTION
In a PCI transaction, a sequence of data items may be transferred in a pipelined fashion between an initiator and a target. The sequence of data items may be transferred either from a host bus buffer (which may be the initiator or the target) to a PCI agent (which is the target or the initiator, respectively) or from a PCI agent to the host bus buffer. For example, a PCI agent could initiate (as the initiator) a data read from the host bus (i.e., the target in this case).
The data items are sequentially clocked between the initiator and the target (e.g., between the initiator buffer and target buffer). The target and initiator each have an associated flow control signal (TRDY# and IRDY#, respectively) that is asserted when the target/initiator is ready for a data item to be transferred. For example, when an initiator initiates a read from a target, the TRDY# signal is asserted when the target is ready to send a data item to the initiator, and correspondingly the initiator asserts an IRDY# when it is ready to receive the data item. Thus, a data item will not be transferred in response to a clock trigger unless both the TRDY# and IRDY# signals are asserted during the clock trigger.
FIG. 1A
shows a sequential storage device
10
, such as a first-in, first-out (“FIFO”) buffer or random access memory (“RAM”) that serves as a data buffer for a target (e.g., the host bus). The device
10
includes a clock input
11
, an active-low chip enable input
13
, and a data output
15
. Also shown is a receiver (e.g., an initiator)
12
having a flow control (e.g., IRDY#) output
14
, a receiver clock input
16
, and a receiver data input
18
for reading data received from the sequential storage device
10
. The data output
15
of the sequential storage device
10
is in communication with the receiver data input
18
of receiver
12
. A clock signal
17
is connected to storage clock input
11
and receiver clock input
16
. In addition, an IRDY# signal
19
is outputted from flow control output
14
and connected to storage chip enable input
13
. The clock signal
17
is a 66 MHZ PCI clock. The IRDY# signal
19
is a flow control signal for controlling the flow of data into the receiver (in this case, initiator)
12
.
FIG. 1B
shows a timing diagram for an illustrative initiator read operation for the sequential storage device
10
of FIG.
1
A. The timing diagram shows a clock signal
17
, an IRDY# signal
19
, output data
215
, and read data
212
which is data read by receiver (initiator)
12
. If the IRDY# signal is asserted concurrent with a clock trigger, the clock trigger causes: (1) the initiator to read the current data item at data output
15
and (2) the sequential storage device
10
to clock the next data item out to data output
15
. If the IRDY# signal is deasserted concurrent with a clock trigger, the initiator does not read the current data item at data output
15
in response to the clock trigger. (It may be assumed for purposes of this illustration that any other necessary control signals, e.g., TRDY#, for transferring data are asserted.)
On one hand, with a 33 MHZ PCI bus, the ERDY# and TRDY# signals provide at least a 6 or 7 nanoseconds (“nsec.”) set-up time prior to a clock trigger. This set-up time is predictably and consistently sufficient for enabling and disabling the sequential storage device
10
. On the other hand, however, the 66 MHZ PCI bus specification (as shown in
FIG. 1B
) guarantees only a 3 nsec. set-up time for TRDY# and RDY# prior to a clock trigger. Unfortunately, 3 nsec. may not be sufficient for consistently enabling and disabling (through the chip enable input
13
) the sequential storage device
10
. Thus, as is shown in
FIG. 1B
, the deassertion (i.e., the IRDY# signal switching from a low state to a high state) of IRDY# during cycle
3
fails to meet the set-up time necessary to ensure that the sequential storage device
10
will not clock out the next data item (Data
4
). Thus, data output from sequential storage device
10
during cycle
4
and thereafter is indeterminate. In addition, this deassertion of IRDY# indicates that the initiator will not read the current data item (Data
3
) at the data output
15
in response to the next clock trigger (clock trigger
4
). During cycle
5
, the IRDY# signal is once more asserted indicating that the initiator will read the current data item (indeterminate data) in response to the following clock trigger (clock trigger
6
), which is the first clock trigger subsequent to the assertion of IRDY#. Consequently, as shown in
FIG. 1B
, the overflow data item (i.e., the data item that was clocked out following the deassertion of the IRDY# signal) in this case Data
3
, may be lost because the initiator failed to read it in response to the fourth clock trigger, which nonetheless may have clocked out the next data item. Also, the sequential storage device
10
may be out of synch with data transfers causing all subsequent transfers to be indeterminate. This loss of the overflow data item occurs regardless of whether the assertion of IRDY# in cycle
5
allows sufficient time to enable the sequential storage device
10
for the following clock trigger (clock trigger
6
).
Accordingly, what is needed is a method and apparatus for transferring a sequence of data items with critically small flow control set-up times from a first sequential storage device to a receiver, such as an initiator buffer. In particular, what is needed is a way to transfer a sequence of data items between an initiator and a target (or vice versa) over a PCI bus when the flow control signals may not provide sufficient set-up times for disabling the source sequential storage device from overflowing an overflow data item in response to a clock trigger following deassertion of a flow control signal.
SUMMARY
One embodiment of the present invention provides a circuit for transferring a sequence of data out of a sequential storage device, which is controlled by a flow control signal that may have an inadequate set-up and hold time. The sequential storage device has a data output to clock out data in response to a flow control signal being asserted. The sequential storage device terminates this clocking out of the data in response to the flow control signal being deasserted. However, overflow or indeterminate data may be relinquished by the sequential storage device and clocked out of the data output even after the flow control signal has been deasserted. The circuit includes a slack register that is connected to the data output of the sequential storage device. The slack register stores the overflow data until the flow control signal is again asserted.


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