Sequential bus architecture

Details Sequential bus architecture Sequential bus architecture

2000-04-21

2003-12-09

Jean, Frantz B (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S020000, C710S036000, C710S038000, C710S316000

Reexamination Certificate

active

06662256

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to bus architectures and, in particular, to a sequential arrangement which consumes minimal space when implemented in hardware, particularly in integrated applications.
BACKGROUND
Various bus architectures have been developed over the years to handle a variety of situations which require the communication of information between individual devices and/or modules in electronic systems. The extent of which certain bus architectures are utilized depends upon a number of factors included the rate of data transfer required to be implemented by the bus, the particular environment in which data transfer is being conducted, and the distance over which data must be transferred.
In computing systems such as personal computers and the like, buses are formed typically by parallel bi-directional arrangements controlled by a microprocessor type device. In some situations, a serial bus may be coupled to a number of devices or modules which relies upon the individual module sensing the availability of the interconnection between the modules and capturing control of the communication link at the time data transmission is available. In such arrangements, there can be only one “talker” on the line but many “listeners”, and require an implementation of collision avoidance arrangements to ensure that data transmitted from one module is unambiguously received by the desired destination module. The foregoing arrangements, while applicable to both printed circuit and integrated applications, each present a variety of advantages and disadvantages to the circuit designer depending upon the specific implementation.
Problems arise in integrated applications where the integrated device may include a number of modules with which communications is desired, such communications being channelled through a single external interface port associated with the integrated device. An arrangement such as this is shown in
FIG. 1
where a single integrated device
10
is shown illustrated which includes a communication module
12
located at or near a periphery of the device
10
and to which an external communication link
14
connects. Within the device
10
are a plurality of modules
16
A-
16
E with which data from the communication link
14
is desired to be transferred. To facilitate this, the communications module
12
includes a number of communications links
18
A-
18
E to the respective modules
16
A-
16
E which provide for the multiplexing of communication signals to the intended module
16
A-
16
E. The links
18
A-
18
E typically comprise a parallel bus arrangement. Where an arrangement similar to
FIG. 1
is implemented in a printed circuit or larger scale application, such an arrangement presents little problem to the electronics designer in terms of the specifics of implementing the various communication links around the printed circuit card or system. However, as illustrated, when the arrangement of
FIG. 1
is integrated into a single electronic chip device, problems arise where the number of individual modules
16
becomes large, thus necessitating a correspondingly large number of links
18
. Where the modules
16
are spread about the integrated device, it becomes architecturally difficult for the integrated circuit designer to provide for the various integrated and wire connections between the modules
16
and the communication interface module
12
. There is also insufficient room on the integrated circuit in the vicinity of the module
12
to allow for convenience and/or economic placement of the communication links.
One solution to this problem is illustrated in
FIG. 2
where a communications arrangement
20
is provided incorporating a ring-bus which interconnects a plurality of modules
24
A-
24
F, each having corresponding connections
26
A-
26
F to the bus
22
Where required, any one of the modules
24
A-
24
F can be configured for communications to an external arrangement and thus the arrangement
20
may be used in both printed circuit and integrated applications. Such an arrangement requires the implementation of tri-state logic to allow coupling to the ring bus
22
. The arrangement of
FIG. 2
becomes problematic, particularly in integrated applications, as the ring bus
22
is required to have connected to it a number of modules all representing varying loads and this may result in transmission problems within the device resulting in difficulties in resolving conflicts such as those mentioned above.
It is an object of the present invention to substantially overcome, or at least ameliorate, one or more of the aforementioned problems and/or provide an alternative bus architecture configuration.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention there is disclosed an internal bus architecture for an integrated circuit device comprising a plurality of modules with which communication is desired via an access port of said device, said architecture comprising:
a plurality of bus segments, each said bus segment interconnecting two of said modules to form a closed loop of said modules connected by said segments; and
a plurality of bus controllers, each said bus controller being associated with a corresponding one of said modules to at least contribute to a unidirectional transfer of communications transactions about said loop, from said access port to a destination one of said modules.
In accordance with another aspect of the present invention there is disclosed a method of communication between an external port of an integrated circuit device and one of a plurality of modules formed with said device, wherein said modules are interconnected by bus segments to form a closed loop, said method comprising the steps of:
(a) forming a communications transaction at said external port, said transaction including a destination address associated with one of said modules;
(b) passing said transaction sequentially via said bus segments between said modules wherein at each said module said destination address is checked for correspondence with an address associated with said module, whereby
(c) if no correspondence is determined, said transaction is passed to a next one of said modules; or
(d) if correspondence is determined, an operation associated with said transaction is performed at said destination address.
Other aspects of the present invention are also disclosed.


REFERENCES:
patent: 4263736 (1981-04-01), Beierwaltes et al.
patent: 4356404 (1982-10-01), Comfort et al.
patent: 4378589 (1983-03-01), Finnegan et al.
patent: 4816993 (1989-03-01), Takahashi et al.
patent: 4922409 (1990-05-01), Schoellkopf et al.
patent: 5347515 (1994-09-01), Marino
patent: 5375097 (1994-12-01), Reddy et al.
patent: 0 186 150 (1986-07-01), None
patent: WO9637984 (1996-11-01), None

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