Sequential activation delay line circuits and methods

Details Sequential activation delay line circuits and methods Sequential activation delay line circuits and methods

2002-12-19

2004-11-09

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S270000

Reexamination Certificate

active

06815989

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2002-21680, filed Apr. 19, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to the field of delay line circuits such as Delay Locked Loops (DLLs), and more particularly, to delay line control circuits and methods for DLLs.
BACKGROUND OF THE INVENTION
In integrated circuit chip Dynamic Random Access Memories (DRAMs), the skew of a clock signal in the integrated circuit chip may affect the operation of the DRAM. A DLL circuit may be used as a compensator for skew of an internal clock signal in a DRAM and/or other integrated circuit chips. The structure and operation of DLLs is well known to those having skill in the art and are described, for example, in U.S. Pat. Nos. 6,459,314; 6,452,432; 6,434,083; 6,388,485; 6,366,148; 6,285,225; 6,222,894; 6,101,137; 5,901,190; and 5,880,612, all of which are assigned to the assignee of the present application.
Unfortunately, a DLL can cause an increase in current consumption in an integrated circuit. Accordingly, in a precharge mode before a DRAM is activated, or in a power-down mode, the DLL is disabled so as to reduce or minimize current consumption of the DLL. In this case, the DLL latches locked phase information in a register, and thus this locked state is maintained.
When the DRAM exits from the precharge mode or power-down mode, all unit delay cells of the DLL selected from locked phase information latched in the register are simultaneously turned on. In this process, a large amount of current may instantaneously flow from an internal supply to a ground voltage of the DLL, and therefore the internal supply voltage of the DLL may become unstable. After all of the selected unit delay cells are simultaneously turned on, the clock signal sequentially passes the selected unit delay cells and a time delay occurs.
FIG. 1
is a block diagram of a conventional delay line control circuit with a delay locked loop (DLL).
FIG. 2
is a logic diagram of control signals used to control unit delay cells shown in FIG.
1
.
Referring to
FIG. 1
, the conventional delay line control circuit
100
with a DLL includes first through sixth unit delay cells DC
1
, DC
2
, . . . , and DC
6
and first through sixth registers REG
1
, REG
2
, . . . , and REG
6
, each of which receives an inverted signal BSTBY of a standby signal, and first through sixth shift turn-on signals ONSFT
1
, ONSFT
2
, . . . , and ONSFT
6
and generates first through sixth control signals CTRL
1
, CTRL
2
, . . . , and CTRL
6
, respectively, used to control the first through sixth unit delay cells DC
1
, DC
2
, . . . , and DC
6
. It will be understood that even though only six of the unit delay cells DC
1
, DC
2
, . . . , and DC
6
and/or six of the registers REG
1
, REG
2
, . . . , and REG
6
are shown in
FIG. 1
, a different number of unit delay cells and/or registers can be used.
Referring to
FIG. 2
, a control signal CTRL that is used to control unit delay cells DCs is generated in response to an inverted signal BSTBY of a standby signal and a shift turn-on signal ONSFT(i−1) stored in a register REG before the DLL is locked. It is seen from
FIG. 2
that the control signal CTRL is activated only if the inverted signal BSTBY of the standby signal and the shift turn-on signal ONSFT(i−1) are activated.
The operation of the conventional delay line control circuit
100
with the DLL will be described with reference to
FIGS. 1 and 2
.
In a precharge mode or power-down mode, the standby signal STBY is at a high level and an inverted signal BSTBY of the standby signal STBY is at a low level. Thus, the first through sixth control signals CTRL
1
, CTRL
2
, . . . , and CTRL
6
of the first through sixth registers REG
1
, REG
2
, . . . , and REG
6
are generated at low levels. Hence, all of the first through sixth unit delay cells DC
1
, DC
2
, . . . , and DC
6
are turned off. However, phase information of the first through sixth unit delay cells DC
1
, DC
2
, . . . , and DC
6
before the DRAM enters the precharge mode or power-down mode are stored in the first through sixth registers REG
1
, REG
2
, . . . , and REG
6
. When the DRAM exits from the precharge mode or power-down mode, the standby signal STBY is at a low level, and the inverted signal BSTBY of the standby signal STBY is at a high level. Since the shift turn-on signal ONSFT(i−1) stored in the first through sixth registers REG
1
, REG
2
, . . . , and REG
6
is at a high level, the first through sixth control signals CTRL
1
, CTRL
2
, . . . , and CTRL
6
are at high levels, and therefore the first through sixth unit delay cells DC
1
, DC
2
, . . . , and DC
6
are activated.
Assuming the first through third unit delay cells DC
1
, DC
2
, and DC
3
are activated before the DRAM enters the precharge mode or power-down mode in
FIG. 1
, if the DRAM exits from the precharge mode or power-down mode, the first through third control signals CTRL
1
, CTRL
2
, and CTRL
3
generated by the first through third registers REG
1
, REG
2
, and REG
3
are at high levels, and therefore the first through third unit delay cells DC
1
, DC
2
, and DC
3
are simultaneously turned on. If the first through third unit delay cells DC
1
, DC
2
, and DC
3
are selected, an internal clock signal INTCK is sequentially transferred to the first through third unit delay cells DC
1
, DC
2
, and DC
3
.
FIG. 3
illustrates an internal circuit of the unit delay cell shown in FIG.
1
. Referring to
FIG. 3
, the unit delay cell includes resistors R connected to supply voltages VCC and first through tenth NMOS transistors MN
1
, MN
2
, . . . , MN
9
, and MN
10
.
In operation of the internal circuit, the fifth NMOS transistor MN
5
and the tenth NMOS transistor MN
10
are turned on in response to a high level of a bias signal VBIAS. If a unit delay cell turn-on signal DCON is applied at a high level, the third NMOS transistor MN
3
, the fourth NMOS transistor MN
4
, the eighth NMOS transistor MN
8
, and the ninth NMOS transistor MN
9
are turned on. If the internal clock signal INTCK is applied at a high level, the first NMOS transistor MN
1
is turned on, the supply voltage VCC is applied to the sixth NMOS transistor MN
6
, and the high level of the supply voltage VCC is output as an output signal OUTCK. If the internal clock signal INTCK is at a high level, an inverted signal BINTCK of the internal clock signal INTCK is naturally at a low level, and thus the second NMOS transistor MN
2
and the seventh NMOS transistor MN
7
are turned off.
If the DRAM exits from the precharge mode or power-down mode and the first through third unit delay cells DC
1
, DC
2
, and DC
3
are simultaneously turned on, the internal clock signal INTCK should pass through the previous first and second unit delay cells DC
1
and DC
2
so that the internal clock signal INTCK is transferred to the third unit delay cell DC
3
. Thus, a time delay occurs, and the first through third unit delay cells DC
1
, DC
2
, and DC
3
are simultaneously turned on, and current consumption is instantaneously increased in the unit delay cells. Hence, the internal supply voltage of the DLL may be unstable. This can be seen from FIG.
3
. If the internal supply voltage of the DLL is unstable, the delay time of the unit delay cells may vary. This may affect a data output time, and further may negatively affect jitter characteristics.
SUMMARY OF THE INVENTION
Delay line circuits and controlling methods according to some embodiments of the present invention include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding unit delay cell is connected to an input of a succeeding unit delay cell. At least two of the unit delay cells in the series are sequentially activated in response to an activation signal. The sequential activation may be performed by a control circuit that is connected to the s

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