Sequencing data on a shared data bus via a memory buffer to...

Details Sequencing data on a shared data bus via a memory buffer to... Sequencing data on a shared data bus via a memory buffer to...

2001-04-26

2003-09-16

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S052000, C710S058000, C711S151000, C711S158000, C711S147000

Reexamination Certificate

active

06622222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to computer memory subsystems, and more particularly to a Dynamic Random Access Memory (DRAM) subsystem. Still more particularly, the present invention relates to a DRAM subsystem that supports speculative reads for efficient utilization of the data out bus.
2. Description of the Related Art
DRAM subsystems are well known in the art. A typical DRAM cell uses the gate capacitance of one or more field-effect transistors to provide the storage of a binary state. The charge on this capacitor will eventually leak and the DRAM cell may change state, causing an incorrect bit to be set or reset in memory. This problem is typically solved by a refresh scheme, which allows the gate of the field-effect transistors to be recharged according to the value stored in the cell, before sufficient discharge has occurred to cause an error.
The typical DRAM is formed by thousands of individual memory cells arranged in a matrix-like configuration. Each DRAM cell includes a capacitor, which is electrically charged or discharged in a “write” operation. The charge establishes a voltage on the capacitor, and the level of the voltage represents a data bit. The data bit represented by the capacitor charge is determined by comparing the capacitor voltage to a threshold reference. Due to the loss of charge associated with the capacitor, a DRAM typically requires its storage cells to be refreshed after each use.
The memory cells of the DRAM matrix are addressed by signals supplied on word lines and bit lines. The word lines extend in a horizontal reference direction in the matrix and connect to the memory cells in the horizontal rows and thus intersect vertical columns of memory cells in the matrix. The bit lines extend in a vertical reference direction in the matrix and connect to the memory cells in vertical columns and thus intersect horizontal rows of cells. By energizing a selected word line, the voltage from the memory cells in the horizontal row corresponding to the selected word line are presented on the bit lines extending from each of the cells.
The DRAM memory array is usually divided into one or more segments, and each of the segments is further divided into bit blocks. Each bit block has a plurality of memory cells, and those memory cells are organized into rows and columns in a matrix. Individual words are selected by addressing the DRAM segments, selecting individual columns in the bit blocks, and selecting the desired word line.
The individual DRAM components are typically four bits wide and are assembled in parallel in a row to create wider DRAM systems. For example, 32 DRAM's may be assembled to form a 16 byte wide data bus. The DRAM system would consist of multiple groups of 32 DRAMS that had a common data bus but each having its own unique address bus. In operation, when a read is issued by the processor, the command will be issued on the address bus to a specific DRAM group and the data is provided to the shared data out bus.
A single data out bus provides the data out for all DRAMs in the DRAM system, while each DRAM has its own address bus. In operation, when a read command is issued by the processor, the command is issued on the address bus to a specific DRAM array and the data is provided to the shared data out bus. If multiple reads are issued, however, with present memory devices, there is no control provided to allow the data to be scheduled to the common data bus, which ultimately leads to situations where there are collisions on the data bus.
During read operations from different DRAMs, the data issued from one DRAM must not run into the data issued from another DRAM on the data out bus. Additionally, some space is needed between accesses to different groups of DRAMs on a common data bus to prevent switching noise.
In general there are three stages in a read access of a group of DRAM'S. The first stage is the access stage, during this stage the address is sent to the DRAM's and the DRAM array is accessed. This stage takes a number of cycles depending on the type and speed of the DRAM's themselves. The second stage is the data transfer which will be some number of cycles depending on the burst length that is requested. The third stage is the precharge stage, in this stage the DRAM is recovering from the access and returning to a state where another access may be initiated. The length of this stage is also dependent on the DRAM type and speed. In general multiple accesses to the same group of DRAMs will result in large gaps between the data packets. To increase data bus utilization multiple groups of DRAMs will be accessed in a overlapping fashion so that the resulting data packets will fill the gaps on the data bus.
Due to the requirement that the reads be scheduled to avoid collisions on the common data bus, the memory controller will have to delay read commands that it received in order to line up the data transfer to a hole on the common data bus. By delaying the read command, the memory controller effectively increases the amount of time that the DRAM group is busy for a given read access, thereby lowering the efficiency of the memory subsystem. If the DRAM access could be started as soon as the memory controller had the command and the data transfer delayed until there was space for it on the bus, the DRAM cycle for the read could be completed earlier, and the group of DRAM's would be available sooner for the next read request.
Another related problem with DRAM operations is that often a read request is issued speculatively and the processor may later resolve that the read should not be completed or that the read address is incorrect. With current memory systems, once a read has been issued by the processor, there is no way for the processor to prevent the data from being issued. However, as described above, the data is usually not issued until a significant number of clock cycles has elapsed after the read request is sent down the processor pipeline. Given the present inefficient utilization of the data out bus, the issuing of data on the data out bus from a read request that is determined to be incorrectly issued prior to placing the data on the bus is a waste of bus resources. There is presently a read command STOP.for SDRAM components; however, there is no mechanism by which a DRAM issued read can be halted after it has been sent by the memory controller.
The present invention recognized that it would be desirable to have a method and DRAM system that provides efficient utilization of the data out bus by allowing controlled speculative reads of data from a DRAM subsystem that enables maximum utilization of the data out bus. A method by which the effects of the delay in data issuance on the data bus that is associated with the refresh operation of a DRAM is substantially reduced would be a welcomed improvement. These and other benefits are provided in the present invention.
SUMMARY OF THE INVENTION
Disclosed is a method and memory subsystem that allows for speculative issuance of reads to a DRAM array to provide efficient utilization of the data out bus and faster read response for accesses to a single DRAM array. Two read requests are issued simultaneously to a first and second DRAM in the memory subsystem, respectively. Data issued from the first DRAM is immediately placed on the data out bus, while data issued from the second DRAM is held in an associated buffer. The processor or memory controller then generates a release signal if the second read is not speculative or is correctly speculated. The release signal is sent to the second DRAM after the first issued data is placed on the bus. The release signal releases the data held in the buffer associated with the second DRAM from the buffer to the data out bus. Because the data has already been issued when the release signal is received, no loss of time is incurred in issuing the data from the DRAM and only a small clock cycle delay occurs between the first issued data and the second issued data on the data

Affiliated with

Also associated with

Rating

Sequencing data on a shared data bus via a memory buffer to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sequencing data on a shared data bus via a memory buffer to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sequencing data on a shared data bus via a memory buffer to... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3082742