Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
1999-02-24
2002-01-29
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S218000, C365S233100, C365S236000
Reexamination Certificate
active
06343355
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sequence controller and more particularly to a sequence controller capable of executing control having an extremely short period and control having a relatively long period with a single circuitry.
2. Description of the Background Art
It is a common practice with a transmission system monitor and control apparatus to collect various kinds of alarm signals from transmission frames, process the collected alarm signals, and send the processed alarm signals to an upper layer apparatus. For example, the monitor and control apparatus outputs an alarm signal on detecting a transmission error once or more every second or on detecting it N consecutive times, and then recovers when not detecting it M or more consecutive times. Because such alarm processing often differs from one apparatus to another apparatus, a microprocessor has heretofore been extensively used in order to flexibly adapt to the alarm processing. However, a microprocessor is not applicable to a monitor and control apparatus of the type monitoring transmission frames having a period of, e.g., 125 &mgr;sec frame by frame and therefore needing high speed processing.
In light of the above, Japanese patent publication No. 120176/1995, for example discloses a programmable controller applicable to an NC (Numerical Control) apparatus. The programmable controller divides process sequences into a group of urgent sequences and a plurality of groups of usual sequences. All of such sequences are cyclically executed with the group of urgent sequences alternating with the group of usual sequences, so that the urgent sequences can be executed at a short period.
However, the above programmable controller relies on a microprocessor whose processing speed is limited. This prevents the programmable controller from being applied to an apparatus required to execute processing at a period as short as 125 &mgr;sec by way of example. Should processing with a short period and processing with a long period each be executed by a respective circuit, the entire circuit scale and therefore the cost would increase.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a sequence controller capable of surely detecting an event occurring at a short period, e.g., the condition of a transmission path and executing, with a single circuitry, processing having a short period to be executed within the above period and processing having a relatively long period.
In accordance with the present invention, a sequence controller includes a memory storing beforehand basic period processing information to be executed at a basic period and time division period processing information to be executed at a time division period which is an integral multiple of the basic period. An address generating circuit continuously generates, at the basic period, addresses for reading the basic period processing information out of the memory and addresses for reading, one block at a time, the time division period processing information at the basic period and reads all of the blocks at the time division period out of the memory.
Also, in accordance with the present invention, a sequence controller includes a memory storing beforehand basic period processing information to be executed at a basic period and a plurality of time division period processing information to be executed at time division periods which are integral multiples of the basic period. An address generating circuit continuously generates, at the basic period, addresses for reading the basic period processing information out of the memory and addresses for reading, one block at a time, the plurality of time division period processing information at the basic period and reads all of the blocks of each of the time division period processing information at a respective time division period out of the memory.
REFERENCES:
patent: 4456967 (1984-06-01), Kuze
patent: 4467458 (1984-08-01), Kuze
patent: 4896266 (1990-01-01), Klashka et al.
patent: 5189671 (1993-02-01), Cheng
patent: 5317724 (1994-05-01), Clippard
patent: 5321350 (1994-06-01), Haas
patent: 5644747 (1997-07-01), Kusuda
patent: 5651128 (1997-07-01), Gaultier
patent: 58-214908 (1983-12-01), None
patent: 7-120176 (1995-12-01), None
Bataille Pierre-Michel
Gluck Jeffrey W.
Kim Matthew
Oki Electric Industry Co. Ltd.
Sartori Michael A.
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