Electrical computers and digital processing systems: support – Synchronization of plural processors
Reexamination Certificate
2006-07-11
2006-07-11
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: support
Synchronization of plural processors
C712S031000
Reexamination Certificate
active
07076676
ABSTRACT:
A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
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Keste Anil S.
Lo Tin-chee
Ng Yuk-Ming
Cantor & Colburn LLP
International Business Machines - Corporation
Kim Kenneth S.
Shkurko Eugene I.
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