Separation method for cutting semiconductor package...

Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure

Reexamination Certificate

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C438S458000, C438S113000, C257S620000, C257SE21596, C257SE21599

Reexamination Certificate

active

11723639

ABSTRACT:
A separation method by which a semiconductor package assemblage is cut in a predetermined width W1along streets arranged in a lattice pattern to separate the semiconductor package assemblage into a plurality of semiconductor packages, the semiconductor package assemblage including a metallic frame having metallic die pads of a predetermined thickness placed in a plurality of rectangular regions defined by the streets, and metallic electrodes of a predetermined thickness placed in the streets and extending in the width direction of the streets, one surface of each die pad and one surface of each electrode being exposed on one surface of the semiconductor package assemblage, whereby each electrode has an intermediate portion in the extending direction removed, and has opposite end portions annexed to the adjacent semiconductor packages. The separation method comprises: a pre-cutting step of forming grooves in the one surface of the semiconductor package assemblage by a rotary cutting blade, each groove having a width W3in each of opposite side edges of a region having a width W2larger than the predetermined width W1in the street, where (W2−2×W3)<W1, and each groove having a depth D larger than the thickness of the electrode; and a main cutting step of cutting the semiconductor package assemblage in the predetermined width W1along the streets by a rotary cutting blade having a thickness corresponding to the predetermined width W1.

REFERENCES:
patent: 6489218 (2002-12-01), Kim et al.
patent: 6841414 (2005-01-01), Hu et al.
patent: 7056768 (2006-06-01), Kameyama et al.
patent: 2005-39088 (2005-02-01), None

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