Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-21
2010-10-26
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S013000
Reexamination Certificate
active
07823117
ABSTRACT:
Various approaches are described for implementing a high-level programming language program in hardware and software components. In one approach, a method comprises compiling the high-level programming language program into a target language program that includes a plurality of functional elements. Execution of the target language program is profiled to obtain execution counts of the functional elements. A subset of the functional elements are selected for implementation in programmable resources of a programmable device based on the profile data and availability of programmable resources. A bitstream is generated to implement a first sub-circuit that performs functions of the subset of functional elements, and the subset of functional elements is removed from the target language program. The programmable device is configured with the bitstream. The target language program is provided for execution by a processor.
REFERENCES:
patent: 5539911 (1996-07-01), Nguyen et al.
patent: 5819064 (1998-10-01), Razdan et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 6205199 (2001-03-01), Polichar et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6606588 (2003-08-01), Schaumont et al.
patent: 7199608 (2007-04-01), Trimberger
patent: 7222314 (2007-05-01), Miller et al.
patent: 7228531 (2007-06-01), Langhammer
patent: 7240303 (2007-07-01), Schubert et al.
patent: 7243330 (2007-07-01), Ganesan et al.
patent: 7315991 (2008-01-01), Bennett
patent: 7340693 (2008-03-01), Martin et al.
patent: 7478031 (2009-01-01), Master et al.
patent: 7490302 (2009-02-01), Rahman et al.
patent: 2004/0139411 (2004-07-01), Smith et al.
patent: 2006/0190905 (2006-08-01), Martin et al.
patent: 2008/0082786 (2008-04-01), Lovell
U.S. Appl. No. 11/197,936, filed Aug. 5, 2005, Tuan et al., entitled “A Programmable Logic Device (PLD) with Memory Refresh Based On Single Event Upset (SEU) Occurrence to Maintain Soft Error Immunity”, Xilinx, Inc., 2100 Logic Drive, CA.
James-Roxby et al., entitled “Time-Critical Software Deceleration in an FCCM”', Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), Apr. 20-23, 2004, ISBN: 0-7695-2230-0,10 pages, Xilinx, Inc., 2100 Logic Drive, San Jose, CA.
Keller et al., entitled “Software Decelerators”, 13th International Field Programmable Logic and Applications Conference (FPL). Lisbon, Portugal, Sep. 1-3, 2003. Lecture Notes in Computer Science 2778. 10 pgs., Xilinx, lnc., 2100 Logic Drive, San Jose, CA.
Levin Naum B
Maunu LeRoy D.
Xilinx , Inc.
LandOfFree
Separating a high-level programming language program into... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Separating a high-level programming language program into..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Separating a high-level programming language program into... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4218648