Separated floating gate for EEPROM application

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257321, H01L 29788

Patent

active

057866147

ABSTRACT:
An EEPROM with separated floating gate to reduce the antenna ratio is disclosed. The structure of the EEPROM includes field oxides formed on a wafer. A control gate is formed in the wafer. A first gate oxide formed above the wafer for isolation. A first polysilicon portion is formed on the first gate oxide, which includes a gate for a transistor, a first contact window and a floating gate. Further, the floating gate is set above the control gate. A second gate oxide is formed on the wafer adjacent to the field oxide for isolation. A tunneling window is formed in the second gate oxide. A second polysilicon portion having a second contact window is formed on the second gate oxide. A dielectric layer is formed on the first polysilicon portion and the second polysilicon portion. Contact holes are formed in the dielectric layer and a connecting structure formed in the contact holes and on the dielectric layer for interconnection.

REFERENCES:
patent: 4019197 (1977-04-01), Lohstroh et al.
patent: 4691216 (1987-09-01), Terada et al.
patent: 5282161 (1994-01-01), Villa
patent: 5576568 (1996-11-01), Kowshik

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