Separate byte control on fully synchronous pipelined SRAM

Details Separate byte control on fully synchronous pipelined SRAM Separate byte control on fully synchronous pipelined SRAM

1999-05-26

2003-07-08

Peikari, B. James (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S168000, C711S104000, C710S021000, C710S033000, C710S061000, C712S027000, C365S238500, C365S233100

Reexamination Certificate

active

06591354

ABSTRACT:

CROSS REFERENCE TO MICROFICHE APPENDIX
Appendix A, which is a part of the present disclosure, is a microfiche appendix consisting of two (2) sheets of microfiche having 116 frames. Microfiche appendix A includes circuit diagrams and chip design diagrams for an embodiment of the invention as implemented on an integrated circuit chip. This and other embodiments are further described below.
CROSS REFERENCE TO RELATED APPLICATION
The following is related to this invention: Ser. No. 08/635,128—Fully Synchronous Pipelined Ram, John R. Mick, now U.S. Pat No. 5,838,631.
BACKGROUND OF THE INVENTION
1. Field or the Invention
The invention relates to memory circuits and, more particularly, to fully synchronous pipelined random access memory circuits with individual byte write capabilities.
2. Background
Synchronous state RAMs (SRAMs) are available for use in high performance systems requiring operation with a fast system clock. Some SRAMs are available which use registers to temporarily store address and control. These SRAMs use a “pipeline” scheme where the address to be accessed is provided during one cycle and, during the next sequential cycle, the data is provided on the data bus. For example, during a read operation, the address from which data is to be read is provided on the nth cycle and the data read from the SRAM is provided on the data bus on the (n+1)th cycle. For write operations, there are SRAMs that provide the address, control and data during the same cycle and there are designs where address and control are provided on the nth cycle and data is provided on the (n+1)th cycle.
The speed of the SRAM is increased by pipelining because the set-up and hold time for a register or latch is typically much shorter than the time to access the main array of the SRAM (the difference typically being several nanoseconds). The result is to break the operations into shorter cycles. On the (n+1)th cycle, the register or latch provides the stored address to the SRAMs main array along with the data to be written to the stored address, meeting the set-up and hold times for writing to the SRAM's main array. The SRAM's cycle time as viewed at the pins of the device can be significantly reduced because of the reduced set-up and hold time for the address and data on the (n+1)th cycle. As a result, the frequency of the system clock can be increased.
One problem with conventional SRAMs is that, typically, trying to intermix reads and writes in a high speed system causes a cycle to be “lost” when a memory write is immediately followed by a memory read (i.e., bus turnaround). Generally, a cycle is lost on turnaround because the structure of these RAMs requires an extra cycle to make sure that all of the data is written into the memory before a read operation can be performed. For example, if a write operation is followed by a read operation from the same address, a lost cycle is needed so that the “new” data will be written to the specified address before the read operation is performed on the data stored at the same address. In systems where bus turnaround occurs frequently, the lost cycles on bus turnaround can significantly reduce the bandwidth of the system. With conventional synchronous SRAMs, the same problem can exist.
The invention disclosed in applicant's prior application, Ser. No. 08/635,128, is a fully synchronous Pipelined RAM with no lost cycles on bus turnaround (i.e., the RAM is capable of performing a read operation during any clock cycle or a write operation during any clock cycle, without limitation). The application disclosed both a “single pipelined” SRAM and a “double pipeline” SRAM. The single-pipelined SRAM includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and control signals during any cycle (referred to as the nth cycle). During a write operation on the nth cycle, the corresponding write data to be written into the SRAM is provided during the next, (n+1)th, cycle. During the nth cycle, the logic circuit causes the previously stored write data to be written from the input circuit into the memory while the new write data is received into the input circuit on the (n+1)th cycle. The write data remains in the logic circuit on any intervening read cycle.
On a read operation, the logic circuit compares the address of the read operation to the address of the most recent write operation. If the addresses match, then the SRAM outputs the data stored in the input circuit; however, if the addresses do not match, the SRAM outputs the data stored in the memory corresponding to the requested read address.
In double pipelined operation, the input circuit is coupled to receive a memory address and control signals during any cycle (the nth cycle) and receives data to be written into the SRAM on the (n+2)nd cycle or outputs data from a read operation on the (n+2)nd cycle. Again, if the address of a read request matches one of the stored write addresses, the corresponding data is outputted through the logic circuit on the (n+2)nd clock cycle.
These devices, however, write whole words of data into memory and are not capable of replacing individual bytes of a word separately.
SUMMARY
According to the present invention, the features included in co-pending Application Serial No. 08/635,128, incorporated here in its entirety, are supplemented with the ability to write selected bytes as well as the entire word to the SRAM. In addition, features also include reading the entire word from the SRAM or from any combination of logic circuitry and memory array storage, as needed, to output the whole word requested by a read operation.
Embodiments of the present invention utilize all bus cycles by internally double pipelining all transactions. The preferred embodiment allows for operation in either single or double pipeline operational mode with the most efficient mode and fastest operation achieved through double pipeline delays. Alternative embodiments of the invention include operation in only double or single pipeline modes.
The user of a device embodying the invention sees a predictable delay (one cycle for single pipeline operation and two cycles for double pipeline operation) for all transactions. There is no requirement placed on what piece of data may be accessed. The device is capable of reading from a combination of the logic circuit and the memory array in order to output the entire word of information requested on a read. The device processes individual bytes of the word.
The operation of these embodiments will be more completely explained below with the Figures and accompanying discussion.


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