Sensing and decoding scheme for a BiCMOS read/write memory

Details Sensing and decoding scheme for a BiCMOS read/write memory Sensing and decoding scheme for a BiCMOS read/write memory

1988-02-16

1989-08-29

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365154, 365177, 365208, 3652256, 36523001, G11C 1908

Patent

active

048624217

ABSTRACT:
A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-AND fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.

REFERENCES:
patent: 4262340 (1981-04-01), Sasaki et al.
patent: 4539659 (1985-09-01), Dumont
patent: 4616342 (1986-10-01), Miyamoto
patent: 4646268 (1987-02-01), Kuno
patent: 4658159 (1987-04-01), Miyamoto
patent: 4723228 (1988-02-01), Shah et al.
Ogiue et al. "A 13ns/500mW 64Kb ECL RAM", Digest of Technical Papers, 1986 IEEE Int'l Solid State Circuits Conf.; (IEEE, 1986), pp. 212-213.

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