Sense mechanism for microprocessor bus inversion

Details Sense mechanism for microprocessor bus inversion Sense mechanism for microprocessor bus inversion

2004-09-22

2008-08-12

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S189080, C365S189090, C365S207000, C365S210100, C365S189180

Reexamination Certificate

active

07411840

ABSTRACT:
A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

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