Sense-amplifying circuit

Details Sense-amplifying circuit Sense-amplifying circuit

1999-10-14

2002-07-30

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S056000

Reexamination Certificate

active

06426657

ABSTRACT:

The present invention relates to a circuit for detecting and amplifying a signal on a single signal line (single-ended signal), more specifically to a circuit (sense-amplifying circuit) for detecting and amplifying the signal having “match”/“non-match” information of a word which is essential in a content addressable memory (hereinafter referred to as a CAM), at the time the signal is still small.
BACKGROUND OF THE INVENTION
Since a single-ended signal line such as a word match line transmits a single-ended signal, ordinary, conventional differential amplifiers cannot be used for detecting and amplifying the signal as they are. Accordingly, it is necessary to modify and improve conventional differential amplifiers so as to be used for detecting and amplifying the single-ended signal.
FIGS. 1 and 2
exemplify a word match line for use in a conventional CAM composed of MOS transistors and its signal detection circuit.
FIG. 1
is one of the most common examples, which is constituted so as to receive the word match line (a sub-word match line in
FIG. 1
) by a primitive logic gate.
FIG. 2
shows a construction constituted by primitive logic gates, but utilizes charge redistributions (charge sharing) among parasitic capacitance in order to achieve a high speed operation.
Although the primitive logic gate circuit typified by the circuit of
FIG. 1
is very simple and small in size, there is the following problems in this type of circuit.
The circuit of
FIG. 1
is confronted with a problem that a signal on the match line is not transmitted to a subsequent stage of the circuit until the potential at the match line traverses the threshold of the logic circuit, so-called “logic threshold”. In other words, there is a problem that the operation speed of the circuit is slow. The slow speed of the operation will be particularly serious when a motion of the match line is slow. To be more specific, the slow speed of the operation will be serious when only one cell among the CAM cells constituting the word drives the match line or when the CAM cells are connected in series to the match line. The speed of this portion of the CAM determines a speed of a search operation of the CAM. Although the logic threshold can partially be controlled by adjusting the sizes of transistors constituting the logic circuit, the logic threshold is limited by the threshold voltage Vt of the transistors.
Moreover, while the match line makes a slow speed transition, a through current flows through the logic circuit that is receiving the match line, with the result that electric power is consumed uselessly. Since the number of the match lines is equal to that of addresses in the CAM, the total of the through current becomes so large that the through current cannot be neglected. The match line must change its level between the level “H” and the level “L” of the CMOS levels, in other words, the match line must change its level between the power supply level and the ground level. This is because if the match line drifts between the power supply level and the ground level, the through current flows through the logic circuit that is receiving the match line. Accordingly, the match line of relatively large capacitance must be charged and discharged between the power supply and the ground potentials. In typical designs of CAMs, input data are sent to the all memory cells so as to be compared with the data that have been already stored therein, and the word match lines at all addresses where the data do not match the input data as the word are forced to be discharged, so that the electric power for charging and discharging the word match line significantly affect the power consumption of the whole CAM circuit. If the total electrostatic capacitance of the word match line is indicated by C; the potential difference between the charged state and the discharged state, V; and the frequency of a search operation, f, the power consumption of the word match line is proportional to the square of the voltage amplitude V, as expressed as fCV
2
, thus a large voltage amplitude of the word match line is very disadvantageous for achieving a low power consumption.
BRIEF SUMMARY OF THE INVENTION
A problem of the circuit of
FIG. 2
arises from the utilization of the charge redistribution (charge sharing) between the parasitic capacitances. This circuit is characterized by its operation that the detection point S is precharged to the power supply level and latched with a half-latch at the start of the search cycle, then the match line and the detection point S are connected to each other after the data are loaded on the bit line, and the level of the detection point S is lowered to the vicinity of the logic threshold at a high speed by the charge sharing. However, in order to detect the level “H” without errors, the capacitance of the detection point S must be designed approximately equal to the parasitic capacitance of the whole designed match line including diffusion capacitances. Accordingly, there is a problem that as the parasitic capacitance of the match line becomes larger as a result of an increase in a width of the word, the detection circuit must be larger in size.
There is another problem in the circuit of
FIG. 2
as follows. In order to enable a search cycle to be performed at the same high speed even when the search cycle just before the search cycle of interest gave a “match” as the case when the previous cycle resulted in a “non-match”, the match line must be once discharged forcibly, causing the electric power to be consumed uselessly. If the match line is not discharged, a search speed varies depending on the operation history, thus the CAM must be designed in accordance with the case where the search speed is the slowest.
The object of the present invention is to solve the foregoing problems. To be more concrete, the present invention is to provide a single-ended signal detection circuit (sense-amplifier) with a high speed and a low power consumption.
According to the present invention, there is provided with a sense-amplifier circuit (
100
) for detecting and amplifying a signal on a single-ended signal line to amplify the signal, which comprises a pair of inverters (
11
,
12
), in which the output terminal of one inverter is connected to the input terminal of the other inverter; and sensing switches composed of first and second switches (
13
,
14
), each of which is connected to a source terminal of corresponding one of the inverters constituting said pair of inverters and to one constant current source (
15
), said first switch being connected to said signal line (
10
) and said second switch being connected to a reference potential (Vref), wherein a driving power of said first switch is larger than that of said second switch.


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patent: 6008673 (1999-12-01), Glass et al.
patent: 6181591 (2001-01-01), Miyatake et al.

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